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8037339 Security device intended to be connected to a processing unit for an audio/video signal and process using such a device  
Example embodiments relate to a security device having two communication interfaces sharing at least one pin, each interface being capable of operating according to either of two predetermined...
8024597 Signal phase verification for systems incorporating two synchronous clock domains  
The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violations in device under test designs comprising two different clock...
8024598 Apparatus and method for clock generation with piecewise linear modulation  
An apparatus and method for generating a clock using piecewise linear modulation are provided. The apparatus includes: a modulation profile generator for outputting an M-bit digital profile...
8024599 Bias and random delay cancellation  
A system and method for digital communication wherein a host provides a host clock and a clockless device transmits to the host a bit stream synchronized according to the clock at a data rate that...
8020026 Phase-aligning corrected and uncorrected clocks  
The present invention relates to providing a system clock signal that is based on either a first clock signal that is capable of being frequency-corrected or a second clock signal that is not...
8020027 Timing control in a specialized processing block  
The tension between fmax and Tco in a specialized processing block of a programmable integrated circuit device can be reduced by providing variable delays on the clock inputs of the pipeline...
8015428 Processing device and clock control method  
A processing device comprises an interface and its control circuit for performing data transfer in synchronization with an external clock, an internal oscillator, and an interface and its control...
8006154 Semiconductor integrated circuit and method for testing semiconductor integrated circuit  
A semiconductor integrated circuit includes a clock generator for generating a second clock signal having a frequency that varies over time by using a first clock signal having a fixed frequency,...
8004329 Hardware performance monitor (HPM) with variable resolution for adaptive voltage scaling (AVS) systems  
An apparatus includes a delay line having multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal through the delay cells....
8006115 Central processing unit with multiple clock zones and operating method  
One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a power supply voltage within the clock...
8001411 Generating a local clock domain using dynamic controls  
A method for generating a local clock domain within an operation includes steps of: receiving a clock frequency measurement for a slow portion of logic within the operation; generating a local...
7996703 Method and apparatus to avoid power transients during a microprocessor test  
Exemplary embodiments provide a computer-implemented method and a system for a startup cycle for a cycle deterministic start. An initializing mechanism applies power to a microprocessor. The...
7996701 Automated clock relationship detection  
Automated clock relationship detection may quickly and reliably detect a clock relationship with minimal latency while reducing problems due to metastability occurring at a solitary instant or...
7996702 System and method for testing overclocking capability of CPU  
A test system for overclocking capability of a central processing unit (CPU) includes a basic input and output system (BIOS), a frequency generator, and a watchdog timer. The BIOS includes an...
7984321 Data transfer control device and electronic instrument  
A data transfer control device includes an OUT-transfer transmitter circuit which transmits OUT data by driving a serial signal line, a clock-transfer transmitter circuit which transmits a clock...
7979732 Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit  
A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis...
7975161 Reducing CPU and bus power when running in power-save modes  
A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more...
7966511 Power management coordination in multi-core processors  
Systems and methods of managing power provide for issuing a first operating requirement from a first processor core and issuing a second operating requirement from a second processor core. In one...
7966512 Data processing device and mobile device  
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
7958383 Computer system with adjustable data transmission rate  
A computer system has an adjustable data transmission rate between a CPU and a core logic chip thereof. In the computer system, the CPU has a power state adjustable in response to a power...
7953998 Clock generation circuit and semiconductor memory apparatus having the same  
A clock generation circuit for a semiconductor memory apparatus includes an internal clock generation unit that receives a clock and generates an internal clock, and a clock selection unit that...
7949133 Controlled cryptoperiod timing to reduce decoder processing load  
Systems and methods are disclosed for enabling encryptor devices to provide real-time messages having offset cryptoperiods according to an offset algorithm within common crypto-sync pulse...
7945803 Clock generation for multiple clock domains  
This disclosure relates to generating clock signals that drive data passing circuitry for various clock domains. Each individual clock domain can adjust its operating frequency from one generated...
7945804 Methods and systems for digitally controlled multi-frequency clocking of multi-core processors  
A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including...
7945805 Architecture for a physical interface of a high speed front side bus  
A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side...
7941583 Controlled frequency core processor and method for starting-up said core processor in a programmed manner  
Embodiments of the invention relate to a driven-frequency processor core. It comprises at least one processor, a non-volatile memory comprising a startup program, a bridge interconnecting buses...
7937605 Method of deskewing a differential signal and a system and circuit therefor  
A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol...
7934115 Deriving clocks in a memory system  
A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing...
7934114 Method of controlling information processing device, information processing device, program, and program converting method  
The method of controlling an information processing device according to the present invention is a method of controlling an information processing device which includes a processor having a cache...
7934113 Self-clearing asynchronous interrupt edge detect latching register  
A digital circuit may have at least two asynchronous clock domains with a controller responsive to a first domain clock signal and a target responsive to a second domain clock signal. A first...
7934039 Variable oscillator for generating different frequencies in a controller area network  
A device suitable for use as a module in a Controller Area Network (CAN) system with a bus or connection includes relatively simple and inexpensive components, including an oscillator that...
7930581 Automation device  
The invention relates to an automation device, with which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The...
7925913 CDR control architecture for robust low-latency exit from the power-saving mode of an embedded CDR in a programmable integrated circuit device  
Clock data recovery (CDR) circuitry of a high-speed serial interface on a programmable integrated circuit device toggles, during the electrical idle period of the receiver of the interface,...
7920663 Using the AC mains as a reference for frequency comparison  
Adjusting a local frequency source is disclosed. A local frequency comparison data is compared with a received frequency comparison data, wherein the local frequency comparison data reflects a...
7921318 Techniques for integrated circuit clock management using pulse skipping  
A processor (400) includes a clock source (402), a central processing unit (CPU) (408), and a clock generator (404). The clock source (402) includes an output for providing a periodic clock...
7921322 Optimize personalization conditions for electronic device transmission rates with increased transmitting frequency  
Systems and/or methods that facilitate expediently transmitting and programming data to an electronic device that contains nonvolatile memory are presented. A host component facilitates the...
7917799 Method and system for digital frequency clocking in processor cores  
Disclosed are a method of and system for digital frequency clocking in a processor core. At least one-processor core is provided, and that processor core has a clocking subsystem for generating an...
7917797 Clock generation using a fractional phase detector  
Circuits are provided that generate from an input signal one or more output clock signals having reduced skew. The input signal has transitions derived from the transitions of an original clock...
7913101 Method and apparatus for treating a signal  
A method includes: delaying an excursion of at least one signal a first number of clock phases when the excursion departs from a value in a first direction; and delaying the excursion of the at...
7913103 Method and apparatus for clock cycle stealing  
A method for producing a plurality of clock signals. The method includes generating a reference clock signal using a phase locked loop (PLL). The reference clock signal is then provided to each of...
7908508 Low power method of responsively initiating fast response to a detected change of condition  
A voltage signal is monitored in comparison to another voltage signal by a differential amplifier. When the first voltage signal value drops below the second voltage signal value an output signal...
7900081 Microcomputer and control system having the same  
A microcomputer includes a main oscillator for generating and outputting a main clock signal, a sub oscillator for generating and outputting a sub clock signal, a central processing unit that...
7895460 Serially connected processing elements having forward and reverse processing time intervals  
Methods and apparatus provide a delayed clock signal to a plurality of serially connected processing elements, such as a bidirectional pipeline processor. The processing elements include forward...
7895461 Clock shifting and prioritization system and method  
A clock shifting and prioritization method comprising adjusting a frequency for a plurality of clocks corresponding to a plurality of respective components of an electronic device based on a...
7890787 Microprocessor programmable clock calibration system and method  
A microprocessor programmable clock calibration device compares, in response to a calibration command from a programmable processor, turns on a normally off reference oscillator clock, compares...
7890684 Two-cycle return path clocking  
Return path clocking mechanism for a system including a master device connected to a plurality of slave devices via a bus. The master device may first generate a global clock. The master device...
7890786 Memory controller and signal synchronizing method thereof  
A memory controller includes an output buffer for receiving a clock signal and outputting the clock signal to an external memory; and a replica buffer for receiving the clock signal and outputting...
7886179 Method for adjusting working frequency of chip  
A method for adjusting the working frequency of a chip is provided. The method detects a frequency adjustment range of a graphic chip when a system is booted. Then, an application program in full...
7882384 Setting and minimizing a derived clock frequency based on an input time interval  
An embodiment of the present invention is directed to a circuit including a data relay stage configurable to receive primary data via a primary data interface, a primary clock having a frequency...
7877623 Method and apparatus for providing symmetrical output data for a double data rate DRAM  
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...