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8233780 Reproducing apparatus and method, and recording medium  
A reproducing apparatus and method includes a reproducing unit to reproduce mainstream data and sub audio data separately added in the mainstream data, wherein the reproducing unit comprises a...
8223106 Display device and driving method thereof  
A driving circuit for a display device includes an input signal generator generating an input signal having one of a plurality of input frequencies corresponding to a respective one of a plurality...
8214668 Synchronizing circuit  
A synchronizing circuit includes an internal partial power supply interruption circuit section which can be subjected to a power supply interruption and includes a data transmission register...
8214563 Host computer, computer terminal, and card access method  
According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received...
8208594 Method and device for clock-data recovery  
A method for the recovery of a clock signal from a data signal is provided where the edges of the signals are each represented as a chronologically-ordered sequence of timing points. In one...
8209562 Double data rate converter circuit includes a delay locked loop for providing the plurality of clock phase signals  
In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a...
8201010 Automatic reference frequency compensation  
In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method...
8199687 Information-communication terminal having function of controlling electric power consumption  
A terminal connected to a wireless communication network includes a BU processor used in wireless communication. An operation mode of the BU processor is switched to one of a sleep mode, a standby...
8201012 Load adaptive EMI reduction scheme for switching mode power supply  
The present invention relates to a frequency jittering device and method, and a switching power supply employing such frequency jittering device. Said method comprises: S1 generating a variable...
8195974 Device and method for synchronizing the states of a plurality of sequential processing units  
A device for providing a plurality of clock signals from a common clock signal. The device includes an input for receiving the common clock signal, a first clock signal path for providing a first...
8195907 Timing adjustment in a reconfigurable system  
This disclosure provides a method for adjusting system timing in a reconfigurable memory system. In a Dynamic Point-to-Point (“DPP”) system, for example, manufacturer-supplied system timing...
8190944 Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed  
A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality...
8185371 Modeling full and half cycle clock variability  
A modeling system includes a processor with software that performs static timing analysis (STA) on a design model. STA software executes a static timing analysis (STA) run with shortened clock...
8185772 Determining execution times of commands  
Methods and apparatuses for determining a number of clock cycles during an execution of a command by a processor, determining a value associated with the number of clock cycles, storing an...
8176351 Sampling mechanism for data acquisition counters  
One or more counter units of a data acquisition device used to perform sampling operations. Each of the counter units is configurable to operate in a selected one of a plurality of modes. During...
8176352 Clock domain data transfer device and methods thereof  
Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also...
8171332 Integrated circuit with reduced electromagnetic interference induced by memory access and method for the same  
The invention provides an integrated circuit with reduced electromagnetic interference induced by memory access. The integrated circuit includes a random code generator, a request receiver and a...
8171330 Asynchronous circuit insensitive to delays with time delay insertion circuit  
The asynchronous circuit insensitive to delays comprises at least one time delay insertion circuit on the propagation path of a signal. The delay insertion circuit comprises, between an input and...
8170164 Transfer clocks for a multi-channel architecture  
A multi-channel architecture comprising a central facility that is under clock control of a central facility's clock signal, and a central transfer clock generator adapted for deriving a central...
8161311 Apparatus and method for redundant and spread spectrum clocking  
An apparatus and method for fault-tolerant and spread spectrum clocking. In one embodiment a master clock synthesizer circuit generates an output clock signal of varying frequency within a...
8156366 Method and apparatus for timing and event processing in wireless systems  
A digital baseband processor is provided for concurrent operation with different wireless systems. The digital baseband processor includes a digital signal processor for executing digital signal...
8150648 Timing generator  
A delay setting data generator generates delay setting data based on rate data. A variable delay circuit delays the test pattern data by a delay time determined by the delay setting data with...
8145935 Clock signal generator for generating stable clock signal, semiconductor memory device including the same, and methods of operating  
A clock signal generator can include a clock signal generation unit that is configured to generate a clock signal. A clock signal control unit is configured to count a number of pulses of the...
8140882 Serial bus clock frequency calibration system and method thereof  
A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both...
8140884 Efficient time-based memory counters  
Some embodiments of efficient time-based memory counters have been presented. In one embodiment, a set of arrays of counters is arranged in layers to associate the set of arrays with a set of...
8136161 3-prong security/reliability/real-time distributed architecture of information handling system  
The present invention is directed to a distributed architecture of an information handling system, including a buried nucleus inaccessible for inspection without heroic means while the buried...
8132040 Channel-to-channel deskew systems and methods  
Systems and methods are disclosed herein to provide channel-to-channel skew control in accordance with one or more embodiments of the present invention. For example in accordance with an...
8132039 Techniques for generating clock signals using counters  
The circuit, typically a delay-locked loop, comprises a phase detector, a first counter, a second counter, and a comparator. The phase detector compares a phase of a first clock signal with a...
8122279 Multiphase clocking systems with ring bus architecture  
Systems and methods for transferring data using a ring bus architecture in a system that implements multi-phase clocking. In one embodiment, the system is a multiprocessor having multiple...
8117482 Timer unit circuit having plurality of output modes and method of using the same  
First and second counter circuits output a signal based on a trigger signal and a clock signal respectively. A selection circuit selects first to fourth signals as the trigger signal, the clock...
8117484 Method and device for generation of out-of-phase binary signals, and use of the same  
A method for the generation of binary signals (So1, So2, So3) which are out-of-phase with a control phase angle (?) which is continuously variable in relation to at least one synchronisation...
8108708 Power optimization when using external clock sources  
Logic circuits of a digital device may be biased to operate over specific external clock frequency ranges by programming a desired clock oscillator frequency range into a configuration memory of...
8103897 Clock generation circuit and semiconductor device including the same  
Objects of the invention are to provide a clock generation circuit, in which, even when different clock signals are used among a plurality of circuits such as a transmitting circuit and a...
8099619 Voltage regulator with drive override  
Techniques to enable voltage regulators to adjust for coming load changes are presented herein. In some embodiments, a functional block such as a microprocessor core having an associated clock...
8099618 Methods and devices for treating and processing data  
A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The...
8095818 Method and apparatus for on-demand power management  
An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system...
8090971 Data recovery architecture (CDR) for low-voltage differential signaling (LVDS) video transceiver applications  
The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is...
8086892 Microcode configurable frequency clock  
A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic...
8086891 Power management of components having clock processing circuits  
A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to...
8082462 Direct synthesis of audio clock from a video clock via phase interpolation of a dithered pulse  
An embodiment of the invention relates to a clock signal generator and a related method to produce a clock signal that is a rational but non-integer submultiple of a reference clock signal by...
8078901 Method for increasing a processor operating frequency when other subsystem demands are low  
A host activity measure indicative of a frequency of disk access commands received by a disk drive is determined, and then compared against a host activity threshold. A subsystem activity measure...
8078900 Asynchronous absorption circuit with transfer performance optimizing function  
A selector is provided so that any one of a plurality of asynchronous absorption paths can be selected when it is assumed that operating frequencies of preceding and succeeding clock domains vary...
8074093 Method and system for optimizing the completion of computing operations  
Computer software that manages the amount of power provided to a processing unit for a specific process task, optimizing the processing speed of that specific task without overheating the...
8073982 Method for setting an operating parameter a peripheral IC and device for carrying out said method  
The invention relates to a method for setting an operating parameter in a peripheral IC. In this method, the operating parameter is transmitted from a central IC via a bus connection to the...
8065549 Scan-based integrated circuit having clock frequency divider  
An integrated circuit includes a clock generator and a synchronous clock circuit unit. The clock generator generates a first clock signal, a second clock signal, and a third clock signal, which...
8055930 Internal clock signal generating circuits including frequency division and phase control and related methods, systems, and devices  
An integrated circuit device may include a main clock signal input pad configured to receive a main clock signal having a main clock frequency, a high speed clock signal input pad configured to...
8054365 Solid-state image pickup device having a signal separation part for separating and providing vertical and horizontal signals and drive method thereof  
A solid-state image pickup device relating to the present invention comprises a pixel area where multiple pixels used for photoelectric conversion of incident light are two-dimensionally arranged....
8040193 Oscillation adjusting circuit and method  
An oscillation tuning circuit is provided and includes a first circuit. The first circuit receives an input data stream with a known time interval, producing a first output signal having a first...
8041979 Method and a system for synchronising respective state transitions in a group of devices  
A method of synchronizing respective state transitions in a group of devices including at least one responding device is disclosed. The group of devices is communicatively coupled to an initiating...
8037336 Spread spectrum clock generation  
The present disclosure provides a spread spectrum clock generation system having a digitally controlled phase locked loop (PLL) and a digital frequency profile generator to create a near optimal...