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8751850 Optimized synchronous data reception mechanism  
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The...
8743633 Integrated semiconductor device  
An integrated semiconductor device including: a first semiconductor device having a clock generation section, first data storage sections storing input data as transfer data, data output terminals...
8738955 Semiconductor device and semiconductor system including the same  
A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to...
8738227 Dark current cutoff system and method for vehicle junction box  
Disclosed is a dark current cutoff system and method for a vehicle junction. In particular, a controller is configured to monitor signal input through a CAN communication module to determine when...
8738949 Power management for processor  
Techniques are generally described related to management of power consumption for a processor. One example method may include identifying a target operating constraint and a first operating...
8732511 Resistor ladder based phase interpolation  
An apparatus comprising a reference circuit, a resistor ladder, and an output circuit. The reference circuit may be configured to generate a reference signal in response to (i) a clock signal,...
8732510 Digital forced oscilation by direct digital synthesis to generate pulse stream having frequency relative to a reference clock signal and to eliminate an off-chip filter  
An opportunity is apparent to develop alternative circuitry. Simplified circuitry without artifacts tied to the clock that drives a digital frequency generator (DFG) is useful in a variety of...
8726062 Data recovery architecture (CDR) for low-voltage differential signaling (LVDS) video transceiver applications  
The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is...
8726057 Power management of components having clock processing circuits  
A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to...
8719616 Method for encoder frequency-shift compensation  
A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a...
8713347 Apparatus and method for masking a clock signal  
A system and method are disclosed for masking a clock input from a clock line when the clock line is not being driven by a clock source. The clock mask is triggered by a clock cycle from the clock...
8713348 Apparatus for performing timer management regarding a system timer scheduler service, and associated method  
An apparatus for performing timer management regarding a system timer scheduler service includes: a processor arranged to control operations of the apparatus; an ordinary timer arranged to provide...
8713345 Apparatus with a local timing circuit that generates a multi-phase timing signal for a digital signal processing circuit  
A local timing circuit receives a reference timing signal and generates a multi-phase timing signal for output to a digital signal processing circuit.
RE44857 Image sensing apparatus and control method thereof  
An image sensing apparatus, having an image sensor for sensing an image of an object and an analog-digital converter which operates at a predetermined frequency and converts an analog signal read...
8707079 Method and apparatus for transmitting data  
A semiconductor device comprising an interface logic module for transmitting data frames across an interface, and controller logic module arranged to control a rate at which the interface logic...
8707080 Simple circular asynchronous clock domain crossing technique for digital data  
A clock domain crossing technique that uses a circular buffer toggled by clocks from the two domains with output metastability protection. The resulting output is a pair of enable signals that may...
8689029 Frequency and voltage scaling architecture  
A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide...
8677173 Method and circuit for trimming an internal oscillator of a USB device  
A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of...
8667320 Deriving accurate media position information  
Various embodiments utilize different counters or clocks, working in concert, to smooth out position information that is derived for a rendering/capturing device. Specifically, in at least some...
8661285 Dynamically calibrated DDR memory controller  
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically...
8656205 Generating reference clocks in USB device by selecting control signal to oscillator form plural calibration units  
A USB device with a clock calibration function and a method for calibrating reference clocks of a USB device are provided. A USB 2.0 initial calibration is performed on the USB device in order to...
8656197 Semiconductor device and control method for semiconductor device  
A semiconductor device includes: a frequency setting information storage unit that stores sets of frequency information indicating setting of a frequency supplied by an oscillation unit and...
8656204 Security device meant to be connected to a processing unit for audio/video signal and method using such a device  
Example embodiments relate to a security device having two communication interfaces sharing at least one pin, each interface being capable of operating according to either of two predetermined...
8648622 Method and device for monitoring a frequency signal  
A method for monitoring a frequency signal provided within a unit is disclosed. The method comprises a step of receiving one or more binary signal levels of a cycle signal (CLK) or a control...
8635486 Apparatus and method of controlling a processor clock frequency  
An apparatus and a method of controlling a processor clock frequency are provided. The apparatus comprises a hardware counter to count write accesses to a memory buffer during a predetermined...
8631266 Semiconductor memory device and method of controlling the same  
A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal;...
8612794 Clock signal generating device and electronic device  
To provide a clock signal generating device that changes the frequency of a predetermined clock signal in a short time and prevents or mitigates instability in the operation of the supply...
8595541 Data processing modules requiring different average clock frequencies having a common clock and a clock gating circuit for deleting clock pulses applied to the modules at times consistent with data sourcing and sinking capabilities  
A method and apparatus are provided for docking data processing modules, which require differing average clock frequencies, and for transferring data between the modules. This comprises a means...
8595538 Single-clock-based multiple-clock frequency generator  
In an embodiment of the present invention, a clock generator circuit is disclosed to include a phase locked loop (PLL) that is responsive to a reference frequency and operative to generate a...
8595542 Explicit skew interface for reducing crosstalk and simultaneous switching noise  
Methods and apparatus are disclosed, such as those involving an inter-chip interface configured to receive and process electronic data. One such interface includes a receiver circuit that includes...
8594575 Shifted channel characteristics for mitigating co-channel interference  
Methods and apparatuses for minimizing co-channel interference in communications systems are disclosed. A method in accordance with the present invention comprises shifting a characteristic of the...
8589718 Performance scaling device, processor having the same, and performance scaling method thereof  
A performance scaling device, a processor having the same, and a performance scaling method thereof are provided. The performance scaling device includes an adaptive voltage scaling unit, a...
8589719 Control apparatus and method, and signal processing apparatus  
A control apparatus controls a signal processing unit. The signal processing unit is mounted within a case and includes a waveform shaping unit which performs a waveform shaping process on an...
8572692 Method and system for a platform-based trust verifying service for multi-party verification  
A method and system for a platform-based trust verifying service for multi-party verification. In one embodiment, the method includes a client platform accessing an service provider over a...
8572419 System-on-chip power reduction through dynamic clock frequency  
A dynamic clock frequency module includes a request evaluation module configured to generate a sum of requests to utilize a system bus from a plurality of modules. A frequency assignment module is...
8566632 Multi-rate sampling for network receiving nodes using distributed clock synchronization  
Various embodiments relate to a network receiver using distributed clock synchronization. The network receiver may include a first timing engine that samples bits received by the receiver with a...
8564330 Methods and systems for high frequency clock distribution  
In accordance with some embodiments, a method for high frequency clock distribution in a VLSI system includes splitting an original master clock signal into one or more pairs of lower-frequency...
8560875 Apparatus for clock calibrating a less precise second clock signal with a more precise first clock signal wherein the first clock signal is inactive during a sniff mode and the second clock signal is active during a sniff mode  
An apparatus for clock calibration on a remote device includes a first oscillator, a second oscillator, and a clock calibration module. The first oscillator generates a first clock signal during...
8549339 Processor core communication in multi-core processor  
Embodiments of the disclosure generally set forth techniques for handling communication between processor cores. Some example multi-core processors include a first set of processor cores in a...
8549286 Method and system for forwarding data between private networks  
In the field of communications technology, a method and a system for forwarding data between private networks are provided, which can enable terminals in different private networks to securely...
8549344 Method for reducing electromagnetic emissions in a multiple micro-controller device  
A method for reducing electromagnetic emissions in an electronic device having a multiple micro-controllers includes identifying the number of micro-controllers installed in the electronic device....
RE44494 Processor having execution core sections operating at different clock rates  
A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations...
8527796 Providing adaptive frequency control for a processor using utilization information  
In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock...
8516292 Method and apparatus for providing symmetrical output data for a double data rate DRAM  
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...
8516293 System and method for implementing a cloud computer  
One embodiment is a clocking system for a computing environment. The system comprises a first set of processes executing in a first computing environment; a first local clock mechanism associated...
8510588 Clock generation circuit and semiconductor device including the same  
Objects of the invention are to provide a clock generation circuit and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge...
8510589 Apparatus and method using first and second clocks  
Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of...
8504868 Computer system with synchronization/desynchronization controller  
A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a...
8504867 High resolution clock signal generator  
A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first...
8504862 Device and method for preventing lost synchronization  
A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a...