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6640275 System and method for data transfer between buses having different speeds  
A system for maintaining data flow between buses is provided wherein the bandwidth of a first bus is less than the bandwidth of a second bus. The bandwidth of a bus is based on the clock speed of...
6640311 Redundant oscillator and method for generating a regulated signal  
A circuit includes a signal generator and a discriminator. The signal generator generates a plurality of reference signals where a majority of the reference signals have the same phase. The...
6636980 System for launching data on a bus by using first clock for alternately selecting data from two data streams and using second clock for launching data thereafter  
A bus interface apparatus and method are implemented. A pair of data streams is generated from the stream of data to be launched onto a data bus. Each stream is staged along a corresponding data...
6636910 Peripheral device of a portable computer with thermal control circuitry  
A peripheral device with thermal control circuitry is set within a casing of a portable computer. The peripheral device includes at least a peripheral processor set for providing specific...
6633994 Method and system for optimizing data transfers between devices interconnected by buses operating at different clocking speeds  
Disclosed is a method and apparatus for optimizing communication between buses operating at different frequencies. A high speed bus provides communication between high speed devices as well as...
6633965 Memory controller with 1×/M× read capability  
Methods and apparatus for receiving data from memory, the data being associated with a strobe, are disclosed herein. In general, the methods and apparatus provide a memory controller with a means...
6629257 System and method to automatically reset and initialize a clocking subsystem with reset signaling technique  
An initialization/reset circuit automatically resets and initializes a clocking subsystem having a phase locked loop (PLL) within a data processing system. The logic circuit is contained within an...
6629256 Apparatus for and method of generating a clock from an available clock of arbitrary frequency  
An apparatus for and method of generating a clock signal having a desired frequency that is derived from a clock source having any arbitrary,frequency. The mechanism of the present invention...
6622253 Controlling processor clock rate based on thread priority  
The preferred embodiment of the present invention varies the speed of processor execution, including associating a clock rate with each thread in a plurality of threads and executing each thread...
6622254 Method of automatically overclocking central processing units  
The invention provides a method of automatically overclocking CPUs for a computer system by using a frequency generator with functions of tuning frequency and monitoring, and applying a numeric...
6622202 Method and device for operating a RAM memory  
A method of operating a RAM memory having a plurality of memory addresses for storing data, the method being performed with a timing based on clock signals spaced by clock periods and comprising...
6614320 System and method of providing a programmable clock architecture for an advanced microcontroller  
One embodiment of the present invention is a programmable clock architecture for a microcontroller that provides multiple different clocking signal frequencies that may be utilized by one or more...
6606713 Microcomputer including circuitry for detecting an unauthorized stoppage of the system clock signal  
A microcomputer comprises a selecting unit for selecting one of a plurality of clock signals generated by a plurality of clock generating sources according to a selection instruction from a...
6601179 Circuit and method for controlling power and performance based on operating environment  
A power control circuit and corresponding technique for controlling the reduction or augmentation of operating frequency and/or supply voltage utilized by an electronic device. Such control is...
6594772 Clock distribution circuitry to different nodes on integrated circuit with clock coupling circuitry to maintain predetermined phase relation between output and input of adjacent nodes  
Integrated circuit clock circuitry includes several clock nodes at different locations on a chip. Each node includes a clock wave input, a clock wave output and feedback circuitry for maintaining...
6591371 System for counting a number of clock cycles such that a count signal is diverted from a cascaded series of write latches to a cascaded series of erase latches  
A system and method are provided for counting a number of clock cycles. In one embodiment, the system comprises a cascaded series of write latches and a cascaded series of erase latches. The...
6584536 Bus transaction accelerator for multi-clock systems  
A bus transaction accelerator, incorporating an innovative control register and status register circuit. The innovative accelerator allows systems with different clocks to handshake in the...
6578155 Data processing system with adjustable clocks for partitioned synchronous interfaces  
A data processing system (20) having a synchronous interface and partitioned clock and I/O logic controller structure. The system includes a plurality of processing components (22), each having a...
6567868 Structure and method for automatically setting the CPU speed  
The preferred embodiment of the invention has a combination of a detection circuit and executable software. The detection circuit is capable of detecting the removal and replacement of a computer...
6564279 Method and apparatus facilitating insertion and removal of modules in a computer system  
A computer system (10) includes a plurality of hot-plug sockets (30-33), each of which can be selectively uncoupled from a bus (59) during normal system operation, in order to facilitate insertion...
6560661 Data receiver that performs synchronous data transfer with reference to memory module  
A signal receiving system includes a plurality of first receivers and at least one second receiver driven based on a sensing result output from the first receivers, the first receivers driven at...
6553506 Information processing device and electronic equipment  
An objective is to provide information processing device and electronic equipment that is capable of transferring data rapidly while using start-stop synchronization. A communication section (142)...
6550013 Memory clock generator and method therefor  
A memory clock generator apparatus and method are implemented. The memory clock is generated, “open loop,” from a processor clock. The processor clock is gated into, and propagated through a shift...
6546497 SCSI clock stretching  
A SCSI initiator, repeater, or device is provided that stretches an initial assertion of the REQ# or ACK# clock signals on the SCSI bus after a period of inactivity on the SCSI data lines. This...
6539492 System and method for maintaining synchronization in a computer storage system  
A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features...
6535986 Optimizing performance of a clocked system by adjusting clock control settings and clock frequency  
A method of adjusting the operating or timing margin of a clocked system, such as a digital computer or a memory controller, is disclosed. The method may be automated to occur upon every initial...
6535989 Input clock delayed by a plurality of elements that are connected to logic circuitry to produce a clock frequency having a rational multiple less than one  
An apparatus for producing one or more clock signals comprises a plurality of delay elements sequentially connected and logic circuitry connected to several of the plurality of delay elements. A...
6532544 High gain local clock buffer for a mesh clock distribution utilizing a gain enhanced split driver clock buffer  
An on-chip clock distribution system and method which utilizes local clock buffers to provide an improved clock signal distribution while avoiding the disadvantages of conventional central buffer...
6530027 Method for reducing power consumption, and portable electronic device and entertainment system that employ the method  
A portable electronic device and method manage battery-produced power without lowering sound quality for music and other sound effects. In the present invention, an operation clock of the CPU of...
6530030 Apparatus for and a method of clock tree synthesis allocation wiring  
In an apparatus for clock tree synthesis allocation wiring, the wiring is appropriately conducting while minimizing the wiring cost and power consumed in operation. A first file stores therein...
6526518 Programmable bus  
The present inventions provide apparatuses and methods for implementing a programmable bus. A programmable bus provides greater functionality and versatility through the ability to manage data...
6519706 DSP control apparatus and method for reducing power consumption  
A digital signal processor (DSP) control apparatus includes a DSP, estimation unit, calculation unit, and clock generator. The DSP performs digital signal arithmetic processing using a clock...
6513123 Power saving control by predetermined frequency slot timing signal based start index and halt instruction termination signal  
The present invention is directed to a power control circuit for reducing wasteful power consumption of an electronic apparatus such as a digital signal processor. More specifically, a preferred...
6513125 Multi-phase multi-access pipeline memory system in which the pipeline memory can decode addresses issued by one processor while simultaneously accessing memory array by other processor  
A multi-phase, multi-access pipeline memory system includes a number, n, of processors; a pipeline memory including a latch; and a bus for interconnecting the processors and pipeline memory; a...
6513126 SYSTEM FOR MODELING A PROCESSOR-ENCODER INTERFACE BY COUNTING NUMBER OF FAST CLOCK CYCLES OCCURING IN ONE SLOWER CLOCK CYCLE AND TRIGGERING A DOMAIN MODULE IF FAST CLOCK REACHES THE CORRESPONDING NUMBER OF CYCLES  
An interface is provided between a digital signal processor or the like and an output encoder or the like that is capable of counting a system clock of the digital signal processor, generally...
6513127 Frequency difference detector with programmable channel selection  
An apparatus comprising a first circuit configured to present one or more control indication signals and (ii) a control clock signal in response to (i) one or more select signals, (ii) one or more...
6513124 Method and apparatus for controlling operating speed of processor in computer  
The number of executed instructions (Iu) in a user mode as one of performance indexes of a computer, and the total number of executed instructions (It) as one of power consumption indexes are...
6510473 Apparatus and method for automatically selecting an appropriate signal from a plurality of signals, based on the configuration of a peripheral installed within a computing device  
An improved computer clock circuit capable of automatically detecting the internal clock frequency of a peripheral component installed in a peripheral component interconnect (PCI) slot, and...
6502202 Self-adjusting multi-speed pipeline  
A self-adjusting multi-speed pipeline in accordance with the present invention is disclosed. A self-adjusting multi-speed pipeline is aware of the required processing time of the slowest among the...
6502201 Determination of frequency of timer ticks  
A method and implementing computer system is provided in which the actual frequency of system timing signals is determinable. In one example, an output from a programmable interrupt timer is...
6493593 Electronic control unit  
An electronic control unit includes a first microprocessor monitoring the operation of a second microprocessor and has a monitoring operation blocking unit for preventing the second microprocessor...
6493830 Clock control device used in image formation  
Video data (default data in case of a black original) output from a CCD line sensor 405 upon reading an image while a light source is kept OFF corresponds to beat noise contained in video data...
6490638 General purpose bus with programmable timing  
A system provides a general purpose bus with programmable timing capability. As part of a microcontroller, this general purpose bus provides a mechanism for communication between general purpose...
6487675 Processor having execution core sections operating at different clock rates  
A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations...
6487647 Adaptive memory interface timing generation  
The invention, in one embodiment, is a method of operating a synchronous memory device generally comprising providing a clock signal to the synchronous memory device to time the operation thereof...
6480954 Method of time multiplexing a programmable logic device  
A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD...
6477659 Measuring timing margins in digital systems by varying a programmable clock skew  
A system that measures timing margins within a digital system by varying a clock skew between components in the digital system. The system receives a reference clock signal as an input. This...
6477657 Circuit for I/O clock generation  
Various apparatuses and methods to generate a clock signal that controls data operations in an integrated circuit. In an embodiment, a circuit for generating a clock signal that controls data...
6477658 Microprocessor with variable clock operation  
A microprocessor with a variable clock operation, which is operative at a highest speed as well as a lowest speed, within a maximum performance range of the microprocessor is disclosed. The...
6477596 Bus controlling method and apparatus for delaying activation of a bus cycle  
With respect to design regarding a bus cycle, it has been necessary to consider a data conflict, if an output disable time of a device is long. A bus controlling unit is installed in a processor....