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6842808 Data exchange between users connected by a bus system and having separate time bases  
A method and device for the exchange of data in messages between at least two users which are connected by a bus system and have separate time bases, the messages containing the data being...
6842825 Adjusting timestamps to preserve update timing information for cached data objects  
In a system including a host, a primary storage subsystem coupled to the host, a cache coupled to the host and separate from the primary storage system, a secondary storage subsystem, and a data...
6842864 Method and apparatus for configuring access times of memory devices  
A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices...
6836852 Method for synchronizing multiple serial data streams using a plurality of clock signals  
Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A...
6834356 Functional clock generation controlled by JTAG extensions  
An on-chip clock generation system used the Serial Interface in an on-chip JTAG facility to write bit patterns in a shift register. The bit patterns are applied to control inputs of a clock...
6820209 Power managed graphics controller  
A controller (or controller chip) providing reduced power consumption without impacting performance is disclosed. The controller monitors activity of components within the controller which require...
6813723 Method of compensating for delay between clock signals  
Method of compensating for a delay between clock signals for a semiconductor integrated circuit having a plurality of devices synchronous to a plurality of clock signals, including the steps of...
6804793 Manipulating an integrated circuit clock in response to early detection of an operation known to trigger an internal disturbance  
A system and method are disclosed which provide an integrated circuit having a clock signal that is dynamically manipulated in response to detected events within the integrated circuit. In one...
6792554 Method and system for synchronously transferring data between clock domains sourced by the same clock  
A method and system for controlling a clock signal is provided. The clock signal is first stored in a storage device. An input representing a clock control signal is input into a first end of a...
6788156 Adaptive variable frequency clock system for high performance low power microprocessors  
A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL)....
6789210 Data processing system having memory including mode register  
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules...
6785832 Process independent source synchronous data capture apparatus and method  
An apparatus for capturing a data signal sent from a transmitting source to a receiving element, the data signal being accompanied by a first clock signal in a source synchronous system. In an...
6775755 Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same  
A coupling circuit for coupling a data signal from a first clock domain defined by a first clock signal to a second clock domain defined by a second clock signal. A phase comparator determines...
6760798 Interface mechanism and method for interfacing a real-time clock with a data processing circuit  
The present invention relates to an interface mechanism and particularly to an interface mechanism for interfacing a real-time clock operating at a first frequency with a data processing circuit...
6754839 UART clock wake-up sequence  
A UART with a clock oscillator that has a sleep mode. A counter is connected to the output of the clock oscillator. When the clock oscillator is awakened, the counter counts up to a specified...
6754745 Method and apparatus for distributing a clock in a network  
A network system is described having multiple network components. The multiple network components include at least one central office (CO) and at least one customer premise equipment (CPE) coupled...
6751743 Method and apparatus for selecting a first clock and second clock for first and second devices respectively from an up-converted clock and an aligned clock for synchronization  
A method and apparatus for synchronizing clocks is provided that is flexible and compensates for process, voltage, and temperature (PVT) variations and other timing differences between two...
6751745 Digital synchronization circuit provided with circuit for generating polyphase clock signal  
A digital synchronization circuit 1000 according to the present invention includes: a polyphase clock generation circuit outputting a plurality of clock signals having the sane frequency and...
6748464 Semiconductor device comprising CPU and peripheral circuit wherein control unit performs wait cycle control that makes peripheral circuit wait a predetermined time before responding to CPU  
A semiconductor device includes a CPU and many peripheral circuits that are accessed by the CPU. Each peripheral circuit includes a wait control register which changeably holds wait cycle number...
6748507 Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory  
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
6745338 System for automatically selecting clock modes based on a state of clock input pin and generating a clock signal with an oscillator thereafter  
An apparatus comprising a circuit configured to automatically select a clock mode in response to a state of a clock input.
6745337 Glitch detection circuit for outputting a signal indicative of a glitch on a strobe signal and initializing an edge detection circuit in response to a control signal  
A glitch detection circuit is described for detecting a glitch on a strobe signal transmitted over a single strobe interface. The glitch detection circuit includes a first input terminal to...
6745369 Bus architecture for system on a chip  
A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all...
6742133 Clock controlling method and clock control circuit  
A novel clock control circuit and method in which phase synchronization with respect to an external clock can be realized without recourse to the external clocks. A clock controlling circuit...
6738922 Clock recovery unit which uses a detected frequency difference signal to help establish phase lock between a transmitted data signal and a recovered clock signal  
A clock recovery unit is used to recover a clock signal from a transmitted data signal. The clock recovery unit includes a phase locked loop (PLL) circuit and a frequency detection circuit. The...
6735712 Dynamically configurable clocking scheme for demand based resource sharing with multiple clock crossing domains  
A first clock signal having a first frequency is applied to drive a first module. A second clock signal having a second frequency is applied to drive a second module. The second frequency is...
6735711 Time frame synchronization of medical monitoring signals  
The present invention provides a system and method for establishing a synchronized time frame for signals in a medical monitoring system. In particular, the present invention provides a system and...
6725391 Clock modes for a debug port with on the fly clock switching  
An integrated circuit constructed for easy debug and emulation includes a function clock circuit and an operation circuit operating in synchronism with a function clock. A trace trigger circuit...
6718474 Methods and apparatus for clock management based on environmental conditions  
A method and apparatus for controlling processor clock rates of a synchronous multi-processor system in response to an environmental condition of a processor. In one embodiment, a...
6715086 Data processing system and method having time-span support for input device driver  
A time-enhanced input device driver for a data processing system is capable of generating time-enhanced output in response to input signals. The input device driver receives a first input-event...
6715089 Reducing power consumption by estimating engine load and reducing engine clock speed  
A computer system has at least one processor and at least one queue for storing instructions for execution by the processor. The processor is capable of being clocked at a plurality of rates. A...
6711694 Apparatus and method for generating a modulated clock signal including harmonics that exhibit a known sideband configuration  
An apparatus and method are provided that helps address the electromagnetic compatibility issues arising from the integration of digital circuitry and analog circuitry within a wireless mobile...
6708287 Active/standby dual apparatus and highway interface circuit for interfacing clock from highway  
A dual apparatus having a first unit and a second unit of a same configuration, one being operated in an active state while the other in a standby state. Each of these first and second units...
6701444 Method and apparatus for process independent clock signal distribution  
A method and apparatus for restoring tracking in a circuit in which gate and metal capacitance vary independently. The present invention allows Shoji balancing to be extended to the situation...
6694444 System and method for reducing over-shoot and ringback by delaying input and establishing a synchronized pulse over which clamping is applied  
In one embodiment of the invention, a clamping circuit clamps an input signal to reduce overshoot and ringback. A pulse generator generates a pulse signal having a pulse interval from the input...
6690224 Architecture of a PLL with dynamic frequency control on a PLD  
An apparatus including a clock generating circuit and a programmable logic circuit. The clock generating circuit may be configured to generate one or more output signals in response to a reference...
6691242 SYSTEM TEST AND METHOD FOR CHECKING PROCESSOR OVER-CLOCKING BY RETRIEVING AN ASSIGNED SPEED FROM AN REGISTER INTERNAL TO THE PROCESSOR, COMPARING WITH RUNNING SPEED, AND DISPLAYING CAUTION MESSAGE TO USER  
The present invention is designed to test whether a Central Processing Unit (CPU) in a computer system is being overclocked. That is, being run at a speed higher than its rated or assigned speed....
6687841 Wide frequency range PLL clock generating circuit with delta sigma modulating circuitry for reducing the time changing ratio of the input voltage of a voltage controlled oscillator  
A clock generation circuit of the present invention extracts a phase error signal of a digital signal obtained from a recording medium (1) by a phase comparator (4), filters the phase error signal...
6687844 Method for correcting clock duty cycle skew by adjusting a delayed clock signal according to measured differences in time intervals between phases of original clock signal  
A device and method to detect and correct clock duty cycle skew detected in high performance microprocessor having a very high frequency clock. The device relies on a delay chain circuit to delay...
6684342 Apparatus and method of dynamic and deterministic changes in clock frequency for lower power consumption while maintaining fast interrupt handling  
An apparatus and method to provide a data processing system with reduced average power consumption while maintaining fast interrupt handling, and/or selectively change clock frequency for...
6680631 Setting the speed of clocked circuitry  
A way is disclosed of establishing at system reset of both physical operating speed limitations imposed on a secondary bus by a circuit layout as well as the speed capabilities of agents attached...
6678834 Apparatus and method for a personal computer system providing non-distracting video power management  
To change the frequency of a video clock without adversely affecting a display quality. To lower the frequency of a video clock, following steps are executed, detecting an opportunity which causes...
6678811 Memory controller with 1X/MX write capability  
Methods and apparatus for writing data to memory are disclosed herein. In general, the methods and apparatus provide a memory controller with means for writing data at different rates. Data may...
6675312 Majority vote circuit for test mode clock multiplication  
A circuit configured to generate an output clock signal generally having (i) a first frequency when in a first mode and (ii) a second frequency when in a second mode, in response to a plurality of...
6675311 Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices  
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing...
6668330 Constant time reference for OS support in different frequency modes  
A method for providing a constant time reference to an operating system includes inputting a PCI clock and inputting a CPU clock. The method outputs a signal having a constant frequency which is a...
6665808 System for generating timing signal varying over time from an ideal signal by combining nominal parameter value signal and parameter variation value signal  
Disclosed is a timing generator including a frequency generator for generating an output signal, and circuitry for providing a nominal parameter setting value to the frequency generator for...
6654900 Method and apparatus for producing multiple clock signals having controlled duty cycles by controlling clock multiplier delay elements  
A method and apparatus for producing multiple clock signals having controlled duty cycles and phase relationships includes processing that begins by generating a plurality of delayed clock signals...
6653867 Apparatus and method for providing a smooth transition between two clock signals  
An apparatus and method is disclosed for providing a smooth transition between a first clock signal at a first frequency and a second clock signal at a lower second frequency. A pulse is generated...
6643792 Integrated circuit device having clock frequency changing function, computer system using the integrated circuit device and clock frequency changing method  
Multi-processor system including processors, a host-PCI bridge, and other devices which are connected to each other by a processor bus and a clock control bus for clock frequency adjustment. Each...