Match Document Document Title
6981168 Clock data recovery system  
A clock data recovery system is provided for resampling a clock signal according to an incoming data signal stream. It comprises a clock generator for generating said clock signal wherein one of...
6978392 Enable propagation controller  
An enable propagation controller employed in an integrated circuit operates in either a sequence manager mode or a transparent mode. When operating in the sequence manager mode, the enable...
6976184 Clock forward initialization and reset signaling technique  
A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates...
6971582 Memory card, digital device, and method of data interfacing between memory card and digital device  
A memory card includes improved data transmission speed. A digital device is capable of data interfacing with memory card for a high speed, and a method for a high-speed data interface between the...
6972609 Semiconductor integrated circuit device with a plurality of internal circuits operable in synchronism with internal clock  
A second clock is generated as an intermittent train of pulses by removing some pulses from a first clock having a predetermined period, and is supplied as an internal clock to internal circuits...
6963373 Image processing apparatus which reduces noise by adjusting the transition timing  
An image processing apparatus which eliminates noise which occurs due to the influence of output from a parallel bus drive circuit added to an output final stage circuit of signal processor or the...
6963992 Method and apparatus to generate clock and control signals for over-clocking recovery in a PLL  
An apparatus comprising a circuit that may be configured to (i) change a frequency of one or more first signals in response to a second signal and (ii) generate a third signal in response to...
6959357 Integrated circuit and method of controlling same  
Bus-connected circuits are made to operate stably and at high speed. A cache memory for high-speed access and a DRAM for low-speed access are connected to a CPU by an address bus, control bus and...
6959398 Universal asynchronous boundary module  
An application specific integrated circuit (ASIC) employs various logic blocks. The blocks may include logic circuits that operate at different clock rates. Consequently, an interface logic block...
6954872 Registering events while clocking multiple domains  
A semiconductor device determines whether a clocking signal intended for latching an event at the designated location is absent, and if so, information about the event that occurred in the absence...
6954843 Data driven information processor capable of internally processing data in a constant frequency irrespective of an input frequency of a data packet from the outside  
A packet generation unit divides a plurality of generated clocks to generate clocks with different frequencies, selects any of the frequencies, sets destination information and data depending on a...
6950958 Method and apparatus for dividing a high-frequency clock signal and further dividing the divided high-frequency clock signal in accordance with a data input  
A method including frequency dividing a high-frequency clock signal into a divided frequency, and further dividing the divided frequency into another divided frequency in accordance with a data...
6948017 Method and apparatus having dynamically scalable clock domains for selectively interconnecting subsystems on a synchronous bus  
In one form, a method for communicating among subsystems coupled to a bus of a computer system on an integrated circuitry chip includes operating subsystems at independent clock frequencies when...
6948085 Method and device for synchronizing processes which are performed on a plurality of units  
A device for synchronizing processes which run on a plurality of units including a central unit linked with other units via a field bus, includes a device provided in the central unit for...
6948087 Wide instruction word graphics processor  
A graphics accelerator includes a vertex input for receiving vertex data, an output for forwarding processed data, and a processor coupled with the vertex input and output. The graphics...
6941485 Clock supply circuit for supplying a processing clock signal used for processing an input signal having a predetermined frequency  
A clock supply circuit capable of supplying clock signals having different frequencies to processing circuits, simplifying the circuit configuration, and realizing a reduction of the power...
6941484 Synthesis of a synchronization clock  
A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external...
6938119 DRAM power management  
A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected memory access rate corresponds to a...
6934870 Clock management scheme for PCI and cardbus cards for power reduction  
A clock management scheme for an 802.11 MAC on a PCI or Cardbus bus that works in conjunction with industry standardized power mechanisms. The scheme involves enabling and disabling the main clock...
6931506 Electronic device for data processing, such as an audio processor for an audio/video decoder  
An electronic device for data processing may include p synchronous processor cores each respectively clocked by one of p clock signals all having a same period T and being phase-shifted by 2π/p...
6931561 Apparatus and method for asynchronously interfacing high-speed clock domain and low-speed clock domain using a plurality of storage and multiplexer components  
Interfacing circuitry for asynchronously transferring data between a high-speed clock domain and a low-speed clock domain is provided. The interfacing circuitry is divided into halves, with one...
6931562 System and method for transferring data from a higher frequency clock domain to a lower frequency clock domain  
A system and method for transferring data from circuitry disposed in a higher frequency clock domain actuated by a first clock signal to circuitry disposed in a lower frequency clock domain...
6928574 System and method for transferring data from a lower frequency clock domain to a higher frequency clock domain  
A system and method for transferring data from circuitry disposed in a lower frequency clock domain actuated by a first clock signal to circuitry disposed in a higher frequency clock domain...
6917365 Processor provided with a slow-down facility through programmed stall cycles  
A processor executes image processing under control of a clock facility, such that a sequence of C effective clock cycles will effect a processing operation of a predetermined amount of image...
6915380 Disk storage system having disk arrays connected with disk adaptors through switches  
A disk storage system has high throughput between a disk adapter of a disk controller and a disk array. The disk adapter of the disk controller is connected to the disk array through switches....
6912605 Method and/or apparatus for implementing security in keyboard-computer communication  
A method for altering timing between transmissions of an input device comprising the steps of (A) receiving a plurality of inputs from the input device, (B) altering the timing between the inputs...
6907487 Enhanced highly pipelined bus architecture  
A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an...
6904539 Method of determining data transfer speed in data transfer apparatus  
A method of determining a transfer speed of an encoded data signal including a clock signal and a data signal is provided. First, the encoded data signal is decoded to generate a decoded clock...
6901528 Minimum latency propagation of variable pulse width signals across clock domains with variable frequencies  
An apparatus comprising a counter circuit, a first register circuit, a second register circuit and an output circuit. The counter circuit may be configured to generate a count signal in response...
6898721 Clock generation systems and methods  
A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; a wireless transceiver transmitting and...
6895523 Generation of pulse signals from a clock signal  
Two first delay signals Q30 and Q34 are generated such that edges thereof are delayed by a first delay time Td1 in relation to the rising edge of a clock signal CLK. Two second delay signals Q32...
6889335 Memory controller receiver circuitry with tri-state noise immunity  
Methods and apparatus are disclosed herein for providing tri-state noise immunity for memory systems such as DDR memory systems, wherein 1) there are large variations in read data loop delay, and...
6889331 Dynamic voltage control method and apparatus  
A dynamic power controller is provided that identifies a clock frequency requirement of a processor and determines a voltage requirement to support the clock frequency requirement. The dynamic...
6889332 Variable maximum die temperature based on performance state  
The maximum performance state available to a processor in a computer system, in terms of operating frequency and/or voltage, changes according to thermal criteria. When the temperature increases...
6886067 32 Bit generic asynchronous bus interface using read/write strobe byte enables  
A display controller having an asynchronous bus interface is provided. In one embodiment a display controller configured to communicate with a microprocessor is provided. The display controller...
6880055 Semiconductor memory device  
So that semiconductor memory devices can be used optimally with regard to different possible operating frequencies, according to the invention, a register area is formed in which frequency...
6876601 Timer facility for a stack or operating system  
A method, comprising the steps of receiving a timeout setting, determining a selected timer unit of one of a first timer unit and a second timer unit, wherein a first set of slots is included in...
6877102 Chipset supporting multiple CPU's and layout method thereof  
A chipset to support multiple CPU's and a layout method thereof. Those independent signal lines for delivering high frequency clock signals of the chipset are isolated from using by other signals...
6874098 Semiconductor integrated circuit  
A semiconductor integrated circuit having one or more functional circuit blocks and executing a set of instructions is configured so as to change the operating frequency or halt operation of said...
6873366 Timing generator for solid-state imaging device  
To reduce the amount of data that should be stored on a memory-built-in timing generator for generating timing pulses for use to drive a solid-state imaging device, V- and H-counters, three ROMs,...
6871292 Sequencer and method of selectively inhibiting clock signals to execute reduced instruction sequences in a re-programmable I/O interface  
A sequencer executes instructions based on a function clock signal to perform I/O functions in a serial peripheral interface based on a source clock signal. The function clock signal has a...
6859886 IO based embedded processor clock speed control  
An input/output controller that allows independent and configurable reduction of clock speeds to its embedded processors when they are not in use to save average power consumption. The processor...
6859884 Method and circuit for allowing a microprocessor to change its operating frequency on-the-fly  
A circuit that permits a processor in a microcontroller to adjust its clock speed on the fly. A processor receives a current clock signal and a phased current clock signal from a speed selection...
6856926 Frequency margin testing of bladed servers  
A frequency margin testing blade is adapted for use in a bladed server. The testing blade is further adapted to provide one or more output clock signals for use as clock inputs to one or more...
6857066 Apparatus and method to identify the maximum operating frequency of a processor  
A method and apparatus comprising setting a register to a value executing a processing instruction to interpret the value and the at least one register verifying that the interpretation of the...
6857037 Extension for the advanced microcontroller bus architecture (AMBA)  
System (50), e.g. a System on a chip (SoC), comprising a system bus (56), a high-speed functional block (51) operably linked to the system bus (56), and a high-speed clock line (54) for applying a...
6848058 Power reduction circuit and method with multi clock branch control  
A power consumption reduction circuit and method utilizes a memory clock source and a memory clock divider circuit that generates divided memory clock output signals as a plurality of...
6845457 Method and apparatus for controlling transitions between a first and a second clock frequency  
A method is provided for controlling transitions between a first and second clock frequency signal in first and second components electrically coupled together and in communication with one...
6845462 Computer containing clock source using a PLL synthesizer  
A computer of the present invention contains: a CPU; plural peripheral devices controlled by the CPU; a data transmission bus between the CPU and the peripheral devices and between the peripheral...
6845454 System and method for selecting between a high and low speed clock in response to a decoded power instruction  
A processor clock generation circuit and related method for a low power consumption modem chip design includes a first clock generator for generating a first clock signal in response to enable and...