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7100066 Clock distribution device and method in compact PCI based multi-processing system  
Disclosed is a clock distribution device and method in a compact PCI system based multi-processing system. A compact PCI based multi-processing system preferably includes processing signals upon...
7096375 Data transfer circuit between different clock regions  
A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives...
7092866 System and method for time compression during software testing  
A technique for applying time compression to simulate long-term execution of a software application in the short time frames includes providing simulated events to a software application under...
7093152 Semiconductor device with a hardware mechanism for proper clock control  
A semiconductor device includes a clock generation unit which generates a clock signal, a first module which asserts a clock-control request signal, and one or more second modules, each of which...
7092478 Local timer which is used in wireless LAN  
A local timer includes a dividing counter which counts a first clock and outputs a reference counting signal divided from the first clock; a timing synchronizing timer which counts a timing...
7093151 Circuit and method for providing a precise clock for data communications  
An apparatus comprising a circuit configured to (i) generate an output having a frequency and (ii) adjust the frequency in response to a measured duration of a known time interval associated with...
7089443 Multiple clock domain microprocessor  
A multiple clock domain (MCD) microarchitecture uses a globally-asynchronous, locally-synchronous (GALS) clocking style. In an MCD microprocessor each functional block operates with a separately...
7085865 I/O throughput by pre-termination arbitration  
The invention provides a method of transmitting data via a bus system coupling a plurality of bus participants with an arbitration procedure for the plurality of bus participants. The invention...
7085874 Synchronous/asynchronous bridge circuit for improved transfer of data between two circuits  
The bridge circuit comprises a first interface circuit operable to receive data from a data source at a first data rate; a second interface circuit operable to transmit the data to a data receiver...
7080276 Circuit and method for automatically selecting clock modes  
An apparatus comprising a circuit configured to automatically select a clock mode in response to a state of a clock input.
7076680 Method and apparatus for providing skew compensation using a self-timed source-synchronous network  
One embodiment of the present invention provides a system that provides skew compensation for communications across a source-synchronous self-timed network. During each clock period, the system...
7076679 System and method for synchronizing multiple variable-frequency clock generators  
In one embodiment, a central processing unit (CPU) includes multiple clock zones. Each clock zone includes at least one sensor that generates a signal indicative of a power supply voltage within...
7073085 Semiconductor circuit device  
To provide a semiconductor circuit device including a synchronous frequency divider which counts input clock signals and outputs a counted value, a selector circuit which receives signals of bits...
7069460 Method and apparatus for image processing with an effective line noise correction  
An image processing apparatus including an image processing circuit, a frequency dispersion circuit, and a timing signal generator. The image processing circuit processes an image signal, and the...
7069461 Closed-loop, supply-adjusted RAM memory circuit  
The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a...
7062394 Performance characterization using effective processor frequency  
An embodiment of the present invention includes a method to analyze processor performance. A processor is saturated with a workload. The processor has a specified operating frequency and a thermal...
7058814 System and method for providing time-limited access to people, objects and services  
A limited tracking system and associated method that enable the use of personal encoded identification media to limit access to tracking information. The tracking system provides concurrent...
7051194 Self-synchronous transfer control circuit and data driven information processing device using the same  
When an instruction decoder decodes an instruction code included in packet data, a copy flag and copy number information are provided to a self-synchronous transfer control circuit. In the...
7051219 System and apparatus for adjusting a clock speed based on a comparison between a time required for a scheduler function to be completed and a time required for an execution condition to be satisfied  
A method of scheduling a CPU in which a clock of the CPU is controlled depending upon the states of processes to reduce power consumption. The clock is controlled by substituting clock functions...
7047433 Method and circuit for synchronizing a higher frequency clock and a lower frequency clock  
A higher frequency clock and a lower frequency clock are locked at a predetermined phase relationship. A total number of pulses of the higher frequency clock occurring between two sequential...
7047432 Method and system for synchronizing output from differently timed circuits  
Synchronizing output from timed circuits includes receiving a first clock signal having a first frequency at a first timed circuit. A first sequence of first circuit values is retrieved from the...
7043655 Redundant clock synthesizer  
A clock architecture employing redundant clock synthesizers is disclosed. In one embodiment, a computer system includes first and second clock boards. The first clock board may act as a master,...
7043656 Methods and apparatus for extending a phase on an interconnect  
Interconnect logic performs a transaction on an interconnect. The transaction may include multiple phases and the interconnect logic may include a counter state machine coupled to an interconnect...
7043652 Calibration method and memory system  
In a memory system having a memory controller 20 and at least one DRAM 30, the memory controller 20 receives a continuous and alternate inversion signal as a pseudo clock signal from the DRAM 30,...
7036038 Converter circuit for synchronizing bus control signals according to a ratio of clock frequencies between different clock domains  
A converter circuit for performing transfer of control logic signals between a first device and a second device in connection with an interconnection bus, the first device operating at the...
7036030 Computer system and method of using temperature measurement readings to detect user activity and to adjust processor performance  
The present invention relates to a computer system and method of using temperature measurements in connection with a computer. In one embodiment, the method includes taking a temperature reading...
7032121 System for deriving desired output frequency by successively dividing clock signal frequency by ratios obtained by dividing clock signal frequency by common divisor and specific integer  
A signal is generated by providing a clock signal having a frequency (fosc). The clock frequency fosc is arithmetically divided by an output frequency (fo) associated with the signal to obtain a...
7028210 System and method for automatically correcting timers  
As provided, a system and method for automatically correcting timers to improve timing accuracy. The system and method provides for the use of inexpensive low tolerance resonators or oscillators...
7020793 Circuit for aligning signal with reference signal  
A signal-aligning circuit includes a phase-adjusting circuit, a first control circuit, a second control circuit, and a tuning circuit. The first control circuit outputs a first voltage signal...
7020788 Reduced power option  
A method and a processor for processing a power mode instruction are provided. The power mode instruction itself includes up to five different sleep modes and one run mode, each for initiating a...
7017064 Calculating apparatus having a plurality of stages  
A calculating apparatus, or system, having a plurality of stages, such as in a pipeline arrangement, has the clocking rail or conductor positioned alongside the stages. With a large number, i.e.,...
7017066 Method, system and synchronization circuit for providing hardware component access to a set of data values without restriction  
The present invention provides hardware-based synchronization within a device such as a set top box so that sets of data values can be communicated between a set of DCR registers operating at a...
7016354 Packet-based clock signal  
In general, in one aspect, the disclosure describes a method for use in packet processing. The method can include receiving at least a portion of at least one packet and, based on the at least a...
7016769 Control device for controlling/regulating the operational sequences in a motor vehicle, and a method of starting such a control device  
A control device and a method for controlling and/or regulating the operational sequences in a motor vehicle, and a method for starting such a control device, which provide a program in a storage...
7013405 Data transfer timing signal apparatus and method of data  
In a data transfer device, a selector selects one of delayed clocks 0 to 3, according to random numbers generated by a random number generating circuit. Output from an output terminal of the...
7012474 System and method generating a delayed clock output  
The system and method generates two clock signals, one with a 2 ns delay with respect to the other, from a single PLL to enable a RGMII.
7012454 Clock shift circuit for gradual frequency change  
A circuit for changing clocks includes a clock generating circuit which generates an output clock signal by controlling a frequency of an original clock signal, and a control circuit which...
7010621 System having a spread-spectrum clock for further suppression of electromagnetic emissions in network devices communicating via a network bus  
A network system includes a network having a network bus, such as unshielded differential twisted-pair wires, electrically connected to a plurality of remote devices, and a network controller for...
7007121 Method and apparatus for synchronized buses  
A bus arbiter controls the bus frequency in a system that includes a plurality of bus masters and a plurality of slaves. The bus frequency is determined according to the internal frequency of the...
7007188 Precision bypass clock for high speed testing of a data processor  
A system clock circuit that provides a high-speed reference clock signal for operating an integrated circuit. The system clock circuit comprises a frequency combiner circuit that receives a first...
7007106 Protocol and method for multi-chassis configurable time synchronization  
Systems and methods are disclosed for time synchronization of operations in a control system. Synchronization networks and devices are provided for transferring synchronization information between...
7003614 Method and apparatus for utilizing different frequencies on a bus based on a number of cards coupled to the bus  
An apparatus and method are provided for operating a PCI-X bus. A device may be provided to determine a number of PCI-X cards coupled to the bus. A mechanism may be provided to control a frequency...
7003681 Programmable logic controller with an auxiliary processing unit  
A programmable logic controller (PLC) with an auxiliary processing unit is disclosed. The conventional PLC with one central processing unit has the problems of low execution speed, low counting...
7003423 Programmable logic resource with data transfer synchronization  
A more time-efficient and area-efficient approach is provided to synchronize the transfer of data into programmable logic resources. A programmable logic resource core clock and a reset signal are...
7000111 Method for masking secret multiplicands  
A mobile terminal for use in a mobile communications system includes a SIM card storing subscriber related data. For security, the SIM card performs secret cryptographic calculations with secret...
6996701 Computer system employing pipeline operation  
A computer system that can be operated by a clock frequency higher than the clock frequency by which the critical path instruction is executed correctly. The pipeline is driven at a high clock...
6990597 Clock generation circuit, data transfer control device, and electronic instrument  
A clock generation circuit capable of generating a high-frequency clock with a simple circuit configuration, together with a data transfer control device and an electronic instrument using the...
6990594 Dynamic power management of devices in computer system by selecting clock generator output based on a current state and programmable policies  
A power management system and method permit the total power consumption by a portable electronic device to be reduced so that the portable electronic device has a longer operating time on a...
6988217 Method and mechanism for generating a clock signal with a relatively linear increase or decrease in clock frequency  
A method and mechanism for generating a clock signal with a relatively linear increase or decrease in clock frequency. A first clock signal is generated with a first frequency which is then used...
6985581 Method and apparatus to verify circuit operating conditions  
A circuit includes an operation unit adapted to perform a circuit operation in a plurality of rounds. The operation unit may operate properly under a predetermined range of operating conditions....