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7257727 Timer systems and methods  
Systems and methods are disclosed for timer architectures. For example, in accordance with an embodiment of the present invention, a timer system includes a prescaler and one or more timer cells...
7254729 Processing system and memory module having frequency selective memory  
A memory module and an apparatus having a memory module for generating an internal clock synchronized to an external clock, the memory module being operated based on the internal clock as an...
7249275 Clock generating device and method for executing overclocking operation  
A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality...
7247955 PWM power supplies using controlled feedback timing and methods of operating same  
A closed loop power converter circuit of a UPS or other power supply includes a pulse width modulator circuit in a forward path of the closed loop power circuit. A compensation circuit provides...
7231537 Fast data access mode in a memory device  
A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the...
7230649 Image sensor system using CMOS image sensor and image sensor apparatus using CMOS image sensor  
An image sensor such as the conventional CMOS image sensor, in which automatic controls including so-called automatic iris control and white balance adjustment for adjusting the sensor...
7222254 System and method for over-clocking detection of a processor utilizing a feedback clock rate setting  
A processor provides a configured clock rate setting for use by a peripheral set. The processor receives back from the peripheral set a feedback clock rate setting. The configured clock rate...
7219252 Apparatus and method for dynamic overclocking  
According to embodiments of the invention, temperature, current, or other physical quantities associated with an integrated circuit, which can also include a processor, may be converted to a...
7219177 Method and apparatus for connecting buses with different clock frequencies by masking or lengthening a clock cycle of a request signal in accordance with the different clock frequencies of the buses  
A method and an apparatus in a computer system for connecting buses with different clock frequencies are provided. The method comprises receiving a request transmitted from a master to a slave. If...
7216249 Clock generation system  
A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a...
7216247 Methods and systems to reduce data skew in FIFOs  
The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the...
7210053 Systems and methods for assigning tasks to derived timers of various resolutions in real-time systems to maximize timer usage  
One or more derived timers based on a source timer are provided to accommodate a plurality of periodic tasks while maintaining the high resolution of the source timer. To accommodate a number of...
7210054 Maintaining processor execution during frequency transitioning  
An embodiment of the present invention includes a standby clock generator and a selector. The standby clock generator generates a standby clock synchronous to a core clock. The core clock is...
7206959 Closed-loop, supply-adjusted ROM memory circuit  
The supply voltage of a memory system is adjusted in response to changes in the frequency of the clock signal. The memory system measures a time from when data becomes valid on the output of a...
7206956 Duty cycle distortion compensation for the data output of a memory device  
A technique for compensating for duty cycle distortion in an output data signal generated by a synchronous dynamic random access memory device (SDRAM) is provided. The output latch of the SDRAM is...
7203859 Variable clock configuration for switched op-amp circuits  
A clock configuration for driving switched op-amp circuits operated in opposite phases is presented in which a common off-phase of variable length is inserted between the on-phases of the...
7200769 Self-compensating delay chain for multiple-date-rate interfaces  
Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock...
7197419 System and method for thermal monitoring of IC using sampling periods of invariant duration  
A system and method are provided for monitoring temperature within a specified integrated circuit. Usefully, the system comprises at least one oscillator device proximate to the integrated circuit...
7197653 Microcontroller for fetching and decoding a frequency control signal together with an operation code  
A microcontroller is realized that is capable of eliminating the time lag required for changing the frequency during operation and of reducing power consumption by accurately and rapidly...
7191353 Coordination of multiple multi-speed devices  
A master device communicating a first range of speeds at which the master device is operable, to a first slave device, the master device and the first slave device determining a second range of...
7191354 Method for synchronizing a first clock to a second clock, processing unit and synchronization system  
The invention relates to a method for synchronizing a first clock C to a reference clock A, the first clock C being connected to said reference clock A via a processing unit B. The invention...
7188146 Navigation apparatus capable of generating and displaying information and method therefor  
In a navigation system in which the page data loaded from a server are displayed in a terminal, the server receiving the request for data loading from the terminal transmits the requested data if...
7184798 Power conservation system and method  
A power management circuit is arranged to apply power to and remove power from its own oscillator to conserve power. A power-on reset circuit provides a power-on-reset signal to a state machine....
7181637 Packet processing system and method for a data transfer node with time-limited packet buffering in a central queue  
A method and system are provided for processing data packets at a data-transfer network node. The method and system include determining a length of time that a packet has been buffered at the node...
7174403 Plural bus arbitrations per cycle via higher-frequency arbiter  
An arbiter in a bus system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or...
7171578 Pulse output function for programmable logic controller with linear frequency change  
Certain exemplary embodiments provide a method for producing pulsed outputs, comprising: automatically changing a first user-specified pulse frequency to a second pulse frequency; and...
7171576 Method, apparatus and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency  
A method, apparatus, and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency. Independent clock signals are generated at...
7171577 Methods and apparatus for a system clock divider  
A power-saving clock divider scheme is cost-effective, flexible, jitterless, and allows the user to keep track of time. In general, the clock divider selectively operates in a normal mode and one...
7167997 Apparatus and method for limiting data transmission rates  
A rate limiting circuit for data stream transmissions provides a generated clock signal to a buffer interposed between source and destination components so as to programmably adjust the maximum...
7165184 Transferring data between differently clocked busses  
A method of asynchronously transferring data from a low speed bus to a high speed bus, comprises latching data at a first predetermined instant in a cycle of the clock frequency of the high speed...
7149914 Clock data recovery circuitry and phase locked loop circuitry with dynamically adjustable bandwidths  
Clock data recovery (CDR) circuitry or phase locked loop (PLL) circuitry can be provided with a dynamically adjustable bandwidth. One CDR circuit or PLL circuit can be provided to support multiple...
7149909 Power management for an integrated graphics device  
In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and...
7146519 Bus clock frequency management based on device bandwidth characteristics  
A frequency manager automatically selects a clock frequency for each device or bus, or for a plurality of devices or buses, in a system, based on various factors and objectives. These factors and...
7139921 Low power clocking systems and methods  
A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of...
7139924 IDE control device suitable for supplying a plurality of requested clock signals to various hard discs  
The present invention discloses an IDE control device suitable for any clock frequency specification. The circuit configuration of the device comprises: a phase-locked loop for receiving clock...
7134033 Clock synchronization apparatus and method of devices with different clocks  
A clock-synchronizing apparatus and method of devices with different clocks are disclosed. Between a first device operated with a first clock and a second device operated with a second clock...
7134037 Method and apparatus for limiting processor clock frequency  
A method and apparatus for limiting a processor clock frequency includes an overclocking prevention circuit. The overclocking prevention circuit includes a frequency limiting circuit having...
7131022 Timing generator system for outputting clock signals to components of an imaging system according to decoded timing control instructions  
A timing generator comprising a programmable program memory that is arranged to comprise program instructions for controlling the generation of timing signals, a timing generator controller for...
7127620 Power analysis resistant coding device  
A coding device for implementing a cryptographic encryption and/or access authorization includes a data processing unit, a decoupling unit, a power supply interface, a main clock supply unit, and...
7124315 Blade system for using multiple frequency synthesizers to control multiple processor clocks operating at different frequencies based upon user input  
In a system and method for managing the operating frequency of processors in a blade-based computer system, a circuit receives a signal with instructions relating to the desired operating...
7120813 Method and apparatus for clock synthesis using universal serial bus downstream received signals  
In one form of the invention, a method for generating a local clock signal responsive to signals on a Universal Serial Bus (“USB”) includes generating a frequency-bearing clock signal by a free...
7114092 Method of supplying a required clock frequency by a clock generator module through interface communication with a mainboard  
A clock generator module is disclosed. A clock generator module, electrically connected with a mainboard through a connector for communicating with each other, wherein an interface definition of...
7111187 Information processor and information processing system utilizing interface for synchronizing clock signal  
An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing...
7110446 Method and apparatus for reducing effect of jitter  
Method and apparatus for reducing effect of jitter is described. More particularly, one or more taps of a delay line are selected for a reference clock signal. These selected taps each have an...
7111122 Access circuit with various access data units  
An access circuit for efficiently accessing a buffer memory in accordance with an instruction from an external circuit. An access data unit for accessing a SDRAM in one operation clock cycle of...
7103790 Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of data  
A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means...
7103793 Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe pad  
A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means...
7100064 Limiting performance in an integrated circuit to meet export restrictions  
An integrated circuit includes at least a first fuse and at least a first processor. Each fuse is in either a conductive state or a non-conductive state. The first processor is configured to...
RE39252 Instruction dependent clock scheme  
A method and apparatus including a first circuit configured to receive multiple instructions including a first instruction having a first execution time, and to generate a first signal having a...
7100012 Processor and data cache with data storage unit and tag hit/miss logic operated at a first and second clock frequencies  
A processor includes a cache memory with a data storage unit operating at a first clock frequency, and a tag unit and hit/miss logic operating at a second clock frequency different than the first...