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7624296 Method and apparatus for synchronizing multiple direct digital synthesizers (DDSs) across multiple printed circuit assemblies (PCAs)  
A radio frequency generating system comprises a synchronization board that receives an external clock signal from a clock source and generates multiple copies of the external clock signal. Each of...
7624295 Processor system, instruction sequence optimization device, and instruction sequence optimization program  
To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a CPU detects mode setting information added to instruction code...
7624293 Synchronization and calibration of clocks for a medical device and calibrated clock  
Apparatus and method support the synchronization and calibration of a plurality of clocks in a medical device system that may provide treatment to a patient with a nervous system disorder. The...
7620862 Method of and system for testing an integrated circuit  
The methods and circuits of the present invention relate to testing integrated circuits. According to one aspect of the invention, a method of testing an integrated circuit is disclosed. The method...
7620839 Jitter tolerant delay-locked loop circuit  
Systems and methods are disclosed herein to provide improved jitter tolerant delay-locked loop circuitry. For example, in accordance with an embodiment of the present invention, an integrated...
7620788 Memory device sequencer and method supporting multiple memory device clock speeds  
A sequence state matrix has a plurality of time slots for storing a plurality of memory device signals. The memory device signals are loaded into the matrix by a sequencer load unit, which loads...
7619449 Method and apparatus for synchronous clock distribution to a plurality of destinations  
Circuits, methods and systems are disclosed providing clock synchronization circuits for synchronized clock distribution for a plurality of devices in a semiconductor device. The clock...
7617431 Method and apparatus for analyzing delay defect  
The apparatus for analyzing a delay defect of the present invention obtains the RC of the maximal incidence among region codes (RCs) to which check circuits detecting errors caused with gradual...
7617410 Simultaneously updating logical time of day (TOD) clocks for multiple cpus in response to detecting a carry at a pre-determined bit position of a physical clock  
A system, method and computer program product for synchronizing adjustment of a time of day (TOD) clock for a computer system having multiple CPUs, each CPU having an associated physical clock...
7617409 System for checking clock-signal correspondence  
A data processing system is provided having a clock signal comparator comprising a reference input port for receiving a reference clock signal and at least a further input port for receiving...
7617339 Serial interface circuit for data transfer  
A serial interface circuit includes a first circuit disposed in the core portion and connected to the CPU, and a second circuit disposed in the peripheral circuit and connected to the peripheral...
7613164 Method and apparatus for generating and distributing an internal clock for radio network controller  
A method for generating an internal clock in a radio network controller and a relevant transmission processing board. The transmission processing board comprises; a clock signal selector for...
7610504 Semiconductor integrated circuit  
A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region...
7610503 Methods for generating a delayed clock signal  
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock...
7610416 Systems and methods for controlling rise and fall times of USB signals  
Systems and methods for controlling the rise and fall times of USB signals for USB devices and peripherals are provided. The rise and fall times of USB peripherals can be controlled, or changed, in...
7610175 Timestamping signal monitor device  
A signal monitor device that detects a signal propagating on a signal line and that generates a timestamp when the signal is detected. The timestamp may be used in a variety of applications...
7606952 Method for operating serial flash memory  
A transmission method for a serial periphery interface (SPI) serial flash includes the steps of providing a first system clock signal and transmitting a plurality of data strings with each two bits...
7603579 Semiconductor chip and semiconductor integrated circuit device for relaying a reference clock from one hard macro to another  
A semiconductor chip has: a plurality of hard macros which operates based on a reference clock; and a clock pad through which the reference clock is supplied from the outside to one of the...
7600167 Flip-flop, shift register, and scan test circuit  
A flip-flop has a first latch and a second latch. The first latch has a first feedback circuit and a first selecting circuit which selects one of a first data input signal and an output signal of...
7600144 Data transmission error reduction via automatic data sampling timing adjustment  
A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and...
7600143 Method and apparatus for variable delay data transfer  
A method and apparatus allows data to traverse a cache interface device in one of four transfer modes. A fast bypass mode provides received cache data within the same master clock cycle as it was...
7600141 Data processing performance control  
A data processing system is provided having a processor 46 which generates control signals for controlling further circuits, such as a clock generator 4 and voltage controller 6 , to operate...
7599459 Receiving apparatus, data transmission system and receiving method  
A receiving apparatus receives data sequences, each of which includes plural data blocks, from plural transmission lines, respectively. The apparatus includes plural elastic buffers and a deskew...
7596711 Method and network for synchronistic processing and providing data using an extrapolation data set including at least one update time point  
A method for synchronously providing data on distributed devices of a network includes storing, by a master device, an extrapolation data set including at least one update time point. The update...
7596669 Apparatus and method for managing memory in a network switch  
The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a...
7590880 Circuitry and method for detecting and protecting against over-clocking attacks  
The present invention is directed to circuitry for detecting and protecting against over-clocking attacks on hardware modules. The circuitry preferably comprises a test signal, a delay path for...
7590789 Optimizing clock crossing and data path latency  
In one embodiment, the present invention includes a method for transmitting a predetermined data pattern from a first agent to a second agent of an interface, receiving an indication of correct...
7587621 Computer system management and throughput maximization in the presence of power constraints  
Methods are provided for maximizing the throughput of a computer system in the presence of one or more power constraints. Throughput is maximized by repeatedly or continuously optimizing task...
7581132 System and method for configuring a microcontroller clock system  
A method is provided for configuring a microcontroller clock system that includes a main oscillator, a phase locked loop, and a backup oscillator. According to the method, the main oscillator and...
7577862 Self adjusting clocks in computer systems that adjust in response to changes in their environment  
An electronic device such as a computer, circuit board, or integrated circuit is built including circuitry for receiving temperature information. The clock frequency of the electronic device is...
7577861 Duty cycle rejecting serializing multiplexer for output data drivers  
A method and apparatus is described herein for serializing input data streams into an output data stream. A first and second input data stream are sampled upon rising edges of a first and second...
7574613 Scaling idle detection metric for power management on computing device  
A component of a computing device such as a processor is operated based on a clock signal oscillating at a frequency. Power management for the computing device is performed by adjusting the...
7573932 Spread spectrum clock generator  
A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number...
7573914 Systems and methods for synchronizing time across networks  
By equipping receiving devices in a network with synchronizable clocks it is possible to periodically send an “impulse” signal that is received by all of the clocks at the same (or relatively...
7571342 Processor system, instruction sequence optimization device, and instruction sequence optimization program  
To reduce power consumption of a processor system including a plurality of processors without degradation of the processing ability, a flag detecting section detects an assignment control flag and...
7571340 Eliminating receiver clock drift caused by voltage and temperature change in a high-speed I/O system that uses a forwarded clock  
Integrated circuits include clock deskew circuitry. The clock deskew circuitry, at the receiver side, receives data signals and a forwarded clock signal from a transmitter. The receiver detects a...
7571339 Clock recovery system with triggered phase error measurement  
A measurement system includes a clock recovery system and a measurement module coupled to the clock recovery system. The clock recovery system has an associated response characteristic. The clock...
7571338 Determining a time difference between first and second clock domains  
Buffer circuitry receives data to be processed by electronic circuitry using a first clock signal associated with a first clock domain. The buffered data is output using a second clock signal...
7571076 Performance monitor device, data collecting method and program for the same  
A performance monitor device includes an input unit to input both of address information and event occurrence information, an address mask unit to determine an address area to which each piece of...
7570669 Synchronizing packet traces  
A system and method for determining a common time base among nodes in a network by iteratively propagating timing constraints among the nodes, and determining a time-shift to apply to the time base...
7568118 Deterministic operation of an input/output interface  
In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock...
7565564 Switching circuit and method thereof for dynamically switching host clock signals  
A switching circuit located in a computer system is disclosed in the present invention. The switching circuit comprises a first phase-locked loop generating a first host clock signal, a second...
7562537 Method of determining cooling system effectiveness  
A method and apparatus is disclosed for detecting the ineffectiveness or failure of a fan that is used to cool an electronic device. The method and apparatus use temperatures measured before and...
7562246 Phase controllable multichannel signal generator  
A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second...
7562245 Single chip 3D and 2D graphics processor with embedded memory and multiple levels of power controls  
An apparatus and method is provided for data processing where power is automatically controlled with a feed back loop with the host processor based on the internal work load characterized by...
7562244 Method for data signal transfer across different clock-domains  
In a method for data signal transfer across different clock-domains, including synchronization of a data signal with a current clock-domain where said data signal is processed, the processing of...
7558980 Systems and methods for the distribution of differential clock signals to a plurality of low impedance receivers  
Systems and methods to distribute clock signals using a common bus. In one embodiment, a clock signal distribution system includes: a bus; a transmitter coupled to the bus to drive a clock signal...
7558979 Methods for determining simultaneous switching induced data output timing skew  
A method of determining timing skew between data outputs of a memory device can include writing a predetermined data pattern to a memory device at a first operational frequency that is less than a...
7557849 Processor-controlled timing generator for multiple image sensors  
A versatile analog front end and timing generator (AFE/TG) integrated circuit is capable of supplying horizontal and vertical timing signals to a large number of disparate image sensors. In a first...
7555670 Clocking architecture using a bidirectional clock port  
Embodiments of the invention are generally directed to systems, methods, and apparatuses for a clocking architecture using a bidirectional clock. In an embodiment, a chip includes a bidirectional...
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