Patents in Class 713/401

Matches 1 - 50 out of 851

Match	Document	Document Title
1	8429439	Inter-pair skew adjustment A skew adjustor that can reduce inter-pair skew between differential signals received via a cable is disclosed. In one embodiment, a skew adjustor includes: a skew detector that receives signals...
2	8429438	Method and apparatus for transferring data between asynchronous clock domains An invention is provided for transferring data between asynchronous clock domains. The asynchronous clock domains include a source clock domain operating with a source clock signal and a receiving...
3	8423813	Memory controller and device with data strobe calibration A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS...
4	8407508	Serial bus clock frequency calibration system and method thereof A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a...
5	8407509	Method for compensating for variations in data timing A method for compensating for variations in timing of data sent to a processor on data bit lines relative to a strobe clock sent to the processor on a strobe clock line that can be used in a dual...
6	8405749	Solid-state imaging device, data transfer circuit, and camera system for compensating for circuit variations during image readout To make it possible to appropriately set a capturing timing for a pixel value. For this, the present invention includes a pixel array unit 2 composed of pixels 21 arranged in a row direction and a...
7	8402300	Synchronization of clocks in autonomous components of an MR system and synchronous execution of commands in those components In a device and a method to execute commands in components of an imaging system, in particular of a magnetic resonance tomography system, local clocks in the components are temporally synchronized,...
8	8402303	Method for encoder frequency shift compensation The embodiments disclose a method for encoder frequency-shift compensation, including, determining frequency values of an input encoder signal, analyzing an encoder index clock signal and the input...
9	8402301	Delaying one-shot signal objects A device may include a processor to execute a thread. The processor may be further configured to execute a set of wrappers that are called from within the thread to invoke a set of one-shot signal...
10	8397095	Method and apparatus for synchronizing time of day of terminal in convergent network Provided is a method and apparatus for synchronizing a time of day (TOD) in a convergent network, wherein the TOD is received from a time server connected in the convergent network and is provided...
11	8397098	Method for countervailing clock skew and core logic circuit using the same A method for countervailing clock skew between a first clock signal and a second clock signal in a core logic circuit. The second clock signal is sampled based on the first clock signal in a...
12	8395410	Semiconductor integrated circuit and system of controlling the same According to one embodiment, a semiconductor integrated circuit includes a first circuit, a second circuit, and a signal propagation control circuit. The first circuit is configured to have a first...
13	8392741	Latency control circuit and semiconductor memory device including the same A latency control circuit includes a delay unit configured to delay an input signal for a delay corresponding to a phase difference between an external clock and an internal clock and generate a...
14	8392742	Cyclemaster synchronization in a distributed bridge A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon...
15	8392740	Synchronization of converters having varying group-delays in a measurement system An analog-to-digital-converter (ADC) timing engine may simplify the use of Delta-Sigma ADCs by compensating for the group-delay of the ADC. The compensation may render the group-delay corresponding...
16	8381009	Device and method for power management A device having power management capabilities and a method for power management, the method includes: providing a clock signal and a supply voltage to at least one component of a device; detecting...
17	8375239	Clock control signal generation circuit, clock selector, and data processing device Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock...
18	8375241	Method and system to improve the operations of a registered memory module A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a...
19	8365003	Synchronizing time domain signals in computing system using phase frequency slope value of cross power spectral density Some embodiments of the present invention provide a system that accurately synchronizes signals related to the operation of a computer system. During operation, the system receives a first...
20	8355294	Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations A synchronous data processing system includes a memory module to store data and a memory controller coupled to the memory module. The memory controller includes a clock inverter to receive an input...
21	8332681	Automatic reference frequency compensation In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method...
22	8327180	Data processing device and mobile device A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
23	8321714	Serial controller and bi-directional serial controller A serial controller is adapted to receive an external clock and an input data, and output an inverted clock and an output data. The serial controller includes an inverter, a serial position...
24	8321713	Fast data access mode in a memory device A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the...
25	8316147	Time synchronization of multiple time-based data streams with independent clocks Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data...
26	8316252	Distributed clock gating with centralized state machine control A method, computer program product, and system are provided for controlling a clock distribution network. For example, an embodiment of the method can include programming a predetermined delay time...
27	8300752	Method, circuit, and design structure for capturing data across a pseudo-synchronous interface A structure for performing cross-chip communication with mesochronous clocks. The structure includes: a data delay line; a remote clock delay line; a structure that captures at least one value of a...
28	8301931	Time synchronization of portable devices A portable time transfer device is provided to transfer accurate date/time to reader devices and, thus, the reader devices do not have to be connected to a source of accurate time. A host computing...
29	8295121	Clock buffer and a semiconductor memory apparatus using the same A clock buffer includes a reference enable signal generator configured to generate a reference enable signal enabled in synchronization with a rising edge of a first period of a second clock after...
30	8286022	Intra-pair differential skew compensation method and apparatus for high-speed cable data transmission systems A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with...
31	8285897	Synchronized multichannel universal serial bus The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB...
32	8276014	Stalling synchronisation circuits in response to a late data signal A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronization circuits for capturing and transmitting the data in response to...
33	8271821	Flexible RAM clock enable A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic...
34	8271823	DLL phase detection using advanced phase equalization A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is...
35	8271825	Synchronization devices having input/output delay model tuning elements in signal paths to provide tuning capabilities to offset signal mismatch Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such...
36	8271824	Memory interface and operating method of memory interface A memory interface circuit includes a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node, to a memory through a transmission line; a data...
37	8266467	Data transfer device and data transfer method To provide inter-LSI data synchronized transfer with a transfer throughput satisfying a required performance without causing an operation timing difference of the entire system even when a wiring...
38	8255733	Clock delay and skew control systems and methods A method of providing a clock signal for an embodiment includes performing a calibration for a closed loop control system to determine a control signal value that provides a desired tuning of the...
39	8245071	Method and apparatus of processing data independently and synchronizing and outputting processed data Provided are a method and apparatus for controlling a plurality of data processing modules that process data independently and output the processed data. A method of controlling a first data...
40	8239670	Multi-aspect identifier in network protocol handshake This specification describes technologies relating to a multi-aspect identifier used in a network protocol handshake for establishing a network connection, while providing protection against denial...
41	8230147	Apparatus and method for communicating with semiconductor devices of a serial interconnection A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and...
42	8219844	Methods and systems for emulating a synchronous clear port A synchronous clear emulation circuit is provided. The synchronous clear emulation circuit includes a register having an asynchronous clear port. Moreover, the synchronous clear emulation circuit...
43	8207976	Circuit An embodiment of a circuit includes an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a...
44	8209562	Double data rate converter circuit includes a delay locked loop for providing the plurality of clock phase signals In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a...
45	8201011	Timing optimization for paths in a processor A system and method for efficient timing optimization for asymmetric paths to replicated units. A microprocessor may include multiple instantiations of a processing core. Chip-level interconnects...
46	8201010	Automatic reference frequency compensation In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method...
47	8195972	Jitter precorrection filter in time-average-frequency clocked systems Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis...
48	8190944	Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality...
49	8190722	Synchronization of timestamps to compensate for communication latency between devices Protocol analyzer systems enable synchronization of timestamps and the capture of data across serially chained boxes that are used together to monitor and capture network data. Through experiment,...
50	8189723	Method, circuit, and design structure for capturing data across a pseudo-synchronous interface A method for source synchronous communication. The method includes dynamically adjusting a delay that is applied to a data signal and a remote clock signal until a delayed remote clock signal is...

Matches 1 - 50 out of 851

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