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8707078 Methods and apparatus for trimming of CDR clock buffer using histogram of clock-like data pattern  
Clock buffers in a clock and data recovery (CDR) system are trimmed by receiving a first transmitted clock-like data pattern in a reduced rate mode, locking the CDR using the received version of...
8707001 Method and system for measuring memory access time using phase detector  
Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference...
8707080 Simple circular asynchronous clock domain crossing technique for digital data  
A clock domain crossing technique that uses a circular buffer toggled by clocks from the two domains with output metastability protection. The resulting output is a pair of enable signals that may...
8700943 Controlling time stamp counter (TSC) offsets for mulitple cores and threads  
In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC...
8700818 Packet based ID generation for serially interconnected devices  
Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory...
8687799 Data processing circuit and control method therefor  
When an encryption processing circuit encrypts data, a current flows in the encryption processing circuit. A noise current generated by a noise generation circuit is superimposed on the current...
8687436 Increasing efficiency of memory accesses by selectively introducing a relative delay between the time that write addresses are provided to the memory and the time that write data is provided to the memory  
Systems and methods for reducing delays between successive write and read accesses in multi-bank memory devices are provided. Computer circuits modify the relative timing between addresses and data...
8683252 Method for ensuring synchronous presentation of additional data with audio data  
A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The...
8683253 Optimized synchronous strobe transmission mechanism  
An apparatus that compensates for misalignment on a synchronous data bus, including a resistor network, a transmitting device, and a receiving device. The resistor network indicates an amount to...
8677173 Method and circuit for trimming an internal oscillator of a USB device  
A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of...
8677170 Method for generating a clock signal  
An apparatus for generating a delayed clock signal. The apparatus is a computer system with a processor to which a memory device is coupled. The memory device has a delay clock generator that has a...
8671302 Method and apparatus for wireless clock regeneration  
Methods and systems for operating a wireless clock system for multimedia datastream transmission and display. Source clock frames are compared with a reference clock frames and the clock difference...
8671303 Write-leveling implementation in programmable logic devices  
Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by...
8671301 Method for ensuring synchronous presentation of additional data with audio data  
A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The...
8665913 Communication device to obtain time information  
A communication device that is to be connected to a providing server for providing time information via a network is provided. The communication device includes a congestion-degree obtainer to...
8661274 Temperature compensating adaptive voltage scalers (AVSs), systems, and methods  
Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating...
8661285 Dynamically calibrated DDR memory controller  
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is typically...
8643416 Semiconductor device including a delay locked loop circuit  
A semiconductor device includes a DLL circuit, which comprises: a delay unit generating a second clock signal by delaying a first clock signal; a phase comparator circuit comparing the first clock...
8638137 Delay locked loop  
A semiconductor device includes a delay unit configured to delay an inputted clock to generate a delay clock, a selection unit configured to select and output one of the inputted clock and the...
8631266 Semiconductor memory device and method of controlling the same  
A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal;...
8631267 Adjustable byte lane offset for memory module to reduce skew  
Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for...
8627134 Semiconductor apparatus and local skew detecting circuit therefor  
A local skew detecting circuit for a semiconductor apparatus include a reference delay block located on the center of the semiconductor apparatus, the reference delay block being configured to...
8601231 Semiconductor memory asynchronous pipeline  
An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous...
8595537 DLL phase detection using advanced phase equalization  
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is...
8588355 Timing recovery controller and operation method thereof  
A timing recovery controller capable of performing timing recovery for a data sequence at twice a symbol rate includes a sampler, a timing base device, a timing error detector and a timing lock...
8589720 Synchronizing timing mismatch by data insertion  
The rate at which data is provided by one device and the rate at which that data is processed by another device may differ. For example, a transmitting device may transmit data according to a...
8583957 Clock distribution in a distributed system with multiple clock domains over a switched fabric  
System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the...
8572425 Data processing device and mobile device  
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
8560875 Apparatus for clock calibrating a less precise second clock signal with a more precise first clock signal wherein the first clock signal is inactive during a sniff mode and the second clock signal is active during a sniff mode  
An apparatus for clock calibration on a remote device includes a first oscillator, a second oscillator, and a clock calibration module. The first oscillator generates a first clock signal during an...
8549535 Distributed taskflow architecture  
A method, a system and a product are disclosed for executing a taskflow in a distributed taskflow architecture and for providing the latter. In at least one embodiment, the taskflow is generated by...
8543750 Method for sharing a resource and circuit making use of same  
A method is provided for interfacing a plurality of processing components with a shared resource component. A token signal path is provided to allow propagation of a token through the processing...
8543746 Self-synchronizing data streaming between address-based producer and consumer circuits  
A circuit arrangement and method facilitate the direct streaming of data between producer and consumer circuits (12P, 12C) that are otherwise configured to communicate over an address-based network...
8527803 System and method for multiple backplane time synchronization  
A system and method for synchronizing multiple backplanes within an information handling system are disclosed. An information handling system includes a first controller that may be operable to...
8527804 Architecture and method for eliminating store buffers in a DSP/processor with multiple memory accesses  
A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When...
8516292 Method and apparatus for providing symmetrical output data for a double data rate DRAM  
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...
8516291 Information processing apparatus, data reception device and method of controlling the information processing apparatus  
A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP value so as to output an adjusted clock signal. By synchronizing transmission data with the adjusted clock signal,...
8504863 Drift tracking feedback for communication channels  
A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A...
8504865 Dynamic phase alignment  
A clock signal may be aligned with a data signal by delaying the signals relative to each other until an edge of one signal aligns with an edge of the other signal, and then causing an inversion of...
8504868 Computer system with synchronization/desynchronization controller  
A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a...
8504864 Data sensor coordination using time synchronization in a multi-bus controller area network system  
A method is provided for synchronizing time in an unsynchronized vehicle controller area network system. A master control unit receives a global time from a time synchronization source. The master...
8504788 Memory controller, system and method for read signal timing calibration  
A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory...
8495410 Sampling phase correcting host controller, semiconductor device and method  
One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or...
8495409 Host controller, semiconductor device and method for setting sampling phase  
According to one embodiment, there is provided a host controller, which samples reception data in a VDS mode and an FDS mode, includes a VDS phase register which holds a phase shift amount in the...
RE44383 Method of self-synchronization of configurable elements of a programmable module  
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.),...
8484501 System for delay locked loop control that provides delay interval stabilization  
The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clo...
RE44365 Method of self-synchronization of configurable elements of a programmable module  
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.),...
8484389 AV renderer peripheral with dual inerrupt lines for staggered interrupts  
An audio-video (AV) playback chain and rendering peripheral device 300 for generating two or more interrupts 306, 308 with a programmable delay 304 between them. Such are configured to prevent two...
8429439 Inter-pair skew adjustment  
A skew adjustor that can reduce inter-pair skew between differential signals received via a cable is disclosed. In one embodiment, a skew adjustor includes: a skew detector that receives signals...
8429438 Method and apparatus for transferring data between asynchronous clock domains  
An invention is provided for transferring data between asynchronous clock domains. The asynchronous clock domains include a source clock domain operating with a source clock signal and a receiving...
8423813 Memory controller and device with data strobe calibration  
A memory controller comprises a DQ path, a DQS path, a delay element, a flip flop, and an adjustment unit. The DQ path receives and passes a data signal, and outputs a delayed data signal. The DQS...