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7627772 |
Fast data access mode in a memory device
A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the...
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7624293 |
Synchronization and calibration of clocks for a medical device and calibrated clock
Apparatus and method support the synchronization and calibration of a plurality of clocks in a medical device system that may provide treatment to a patient with a nervous system disorder. The...
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RE40990 |
Data transmission across asynchronous time domains using phase-shifted data packet
A method and apparatus is provided for transmitting multi-bit data across asynchronous time domains. In one embodiment, the apparatus includes a first delay circuit to generate a selector signal...
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7613944 |
Programmable local clock buffer capable of varying initial settings
A programmable local clock buffer for integrated circuit devices which is capable of varying initial settings is provided. The illustrative embodiments allow a single type of local clock buffer...
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7610504 |
Semiconductor integrated circuit
A semiconductor integrated circuit including a first power supply region supplied with a first power supply voltage, and having a first clock distribution network, a second power supply region...
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7610502 |
Computer systems having apparatus for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock...
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7610503 |
Methods for generating a delayed clock signal
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock...
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7606342 |
Tracking the phase of a received signal
The tracking of the phase of a received signal having a known preamble is accomplished by the steps of: initializing a phase-locked loop in accordance with estimated phase parameters, which are...
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7603246 |
Data interface calibration
Embodiments for positioning transitions in one or more data signals in relation to a data strobe signal are disclosed. For an example embodiment, a receiving device may return a test value to a...
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7600144 |
Data transmission error reduction via automatic data sampling timing adjustment
A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and...
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7594133 |
Method and apparatus for determining a deviation between clock pulse devices
The invention relates to a method for synchronizing clock pulse devices. According to this method, an emission unit emits at least one narrow-band distant signal; clock pulse devices of receiving...
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7590879 |
Clock edge de-skew
Circuits, methods, and apparatus for deskewing rising and falling edges of a clock signal. One embodiment of the present invention utilizes a delay element in a data path to adjust a data signal...
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7590880 |
Circuitry and method for detecting and protecting against over-clocking attacks
The present invention is directed to circuitry for detecting and protecting against over-clocking attacks on hardware modules. The circuitry preferably comprises a test signal, a delay path for...
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7584317 |
Protocol conversion circuit
A protocol conversion circuit performing a protocol conversion between a preceding stage circuit and a succeeding stage circuit includes a data storing unit storing input data from the preceding...
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7583106 |
Clock circuitry
A circuit comprising: clock circuitry for supplying a first faster clock signal to a first circuit portion and a second slower clock signal to a second circuit portion, and varying the relative...
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7581131 |
Method and system for balancing clock trees in a multi-voltage synchronous digital environment
A method for balancing clock trees in a multi-voltage synchronous digital environment is provided that includes generating a first source clock signal in a first voltage domain based on a first...
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7580037 |
Techniques for graphical analysis and manipulation of circuit timing requirements
Techniques for organizing and displaying timing data derived from an EDA tool are provided that allows users to easily extract, analyze, and manipulate portions of the timing data relevant to...
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7580524 |
Method and apparatus for synchronizing the emitter and the receiver in an autocompensating quantum cryptography system
In a method and apparatus for synchronizing the receiver and the emitter in an autocompensating quantum cryptography system it is allowed to one of the stations (for example the emitter) to define...
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7573932 |
Spread spectrum clock generator
A spread spectrum clock generator includes a non-volatile memory to store control codes corresponding to a predetermined delay. A delay circuit receives a control code having a predetermined number...
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7574613 |
Scaling idle detection metric for power management on computing device
A component of a computing device such as a processor is operated based on a clock signal oscillating at a frequency. Power management for the computing device is performed by adjusting the...
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7571407 |
Semiconductor integrated circuit and method of testing delay thereof
A semiconductor integrated circuit comprises: a first area, formed on a semiconductor chip, which operates at a first predetermined voltage and a first predetermined frequency; a second area,...
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7568118 |
Deterministic operation of an input/output interface
In one embodiment, the present invention includes a method for receiving data from a second device in a first device, forwarding the data from an input/output (I/O) clock domain to a system clock...
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7565563 |
Non-volatile memory arrangement and method in a multiprocessor device
This invention relates to multiprocessor arrangements with shared non-volatile memory and the design of the access control of this memory, in particular to such memories embedded or integrated into...
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7562246 |
Phase controllable multichannel signal generator
A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second...
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7555590 |
Fast buffer pointer across clock domains
Retiming circuitry for retiming a data signal transmitted from a first environment under control of a first clock signal to a second environment under control of a second clock signal, said first...
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7555667 |
Programmable logic device integrated circuit with dynamic phase alignment capabilities and shared phase-locked-loop circuitry
Adjustable transceiver circuitry is provided for programmable integrated circuits. The transceiver circuitry has a dynamic phase alignment circuit that can be used for aligning clock and data...
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7555668 |
DRAM interface circuits that support fast deskew calibration and methods of operating same
A DRAM interface circuit includes a clock generation circuit configured to generate a plurality of internal clock signals and skew data in response to a plurality of data strobe signals (DQS)...
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7552352 |
Synchronization of signals
A method and system for synchronizing signals. First and second signals are sent (compressed or uncompressed) from a source to a receiving apparatus of a receiving system. The first signal has...
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7549066 |
Automatic power savings stand-by control for non-volatile memory
A non-volatile memory array such as a flash memory array may include a power savings circuit to control a stand-by mode of the non-volatile memory array. The power savings circuit may cause a...
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7549074 |
Content deskewing for multichannel synchronization
The various embodiments of the invention provide an apparatus, system and method for data content deskewing among a plurality of data channels for data synchronization. The various embodiments...
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7543172 |
Strobe masking in a signaling system having multiple clock domains
Systems and methods for masking strobe signals in strobe-based systems are provided below. These strobe-masking systems receive a strobe signal from a component operating under one clock domain and...
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7543201 |
Semiconductor devices including test circuits and related methods of testing
A semiconductor device may include a control signal generator configured to generate a test control signal in response to an externally applied test command signal. First and second transmission...
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7543090 |
Double-pumped/quad-pumped variation mechanism for source synchronous strobe lockout
An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an...
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7543171 |
Method and system for dynamic temperature compensation for a source-synchronous interface
A method for synchronizing a data signal to a clock signal in a source-synchronous system, the source-synchronous system having first and second systems linked by an interface, the first system...
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7539793 |
Synchronized multichannel universal serial bus
The invention provides a method and apparatus for providing a synchronized multichannel universal serial bus, the method in one aspect comprising supplementing the signal channels in the USB...
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7535984 |
Clock adjustment apparatus and method thereof
A clock adjustment apparatus delays a clock signal and adjusts a phase of the signal, thereby increasing or decreasing a delay amount of the clock signal in accordance with a phase relation between...
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7529959 |
System and method for aligning data in a network environment
In a network environment, a first master timing generator generates a first frame reference signal and a second master timing generator generates a second frame reference signal. A first data...
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7526664 |
Drift tracking feedback for communication channels
A communication channel includes a first component having a transmitter coupled to a normal signal source, and a second component having a receiver coupled to a normal signal destination. A...
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7519844 |
PVT drift compensation
A timing circuit for generating a timing signal having a predetermined relationship with a reference signal. The timing circuit includes a locked loop for generating the recovered clock signal,...
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7519139 |
Signal monitoring systems and methods
Systems and methods are disclosed herein to provide signal monitoring techniques. For example, in accordance with an embodiment of the present invention, an integrated circuit includes a phase...
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7509469 |
Semiconductor memory asynchronous pipeline
An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous...
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7506193 |
Systems and methods for overcoming part to part skew in a substrate-mounted circuit
Variable compensation for part to part skew of components in a substrate-mounted circuit is described. The variability may be provided through a computer software program acting on a programmable...
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7506222 |
System for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling
A system for phase tracking and equalization across a byte group for asymmetric control of high-speed bidirectional signaling includes a slave device and a master device that is coupled to the...
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7500129 |
Adaptive communication interface
Embodiments of the invention include a communication interface and protocol for allowing communication between devices, circuits, integrated circuits and similar electronic components having...
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7493509 |
Intra-pair differential skew compensation method and apparatus for high-speed cable data transmission systems
A differential serial communication receiver circuit automatically compensates for intrapair skew between received differential signals on a serial differential communication link, with...
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7489742 |
System and method for clock recovery in digital video communication
A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive...
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7490257 |
Clock distributor for use in semiconductor logics for generating clock signals when enabled and a method therefor
A clock distributor circuit is provided which works with power consumption reduced in semiconductor logic circuitry including clock synchronous circuits. The clock distributor circuit includes...
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7490258 |
Data processing device and mobile device
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
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7487377 |
Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer
Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and...
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7486126 |
Semiconductor integrated circuit with pulse generation sections
This invention provides a technique for enhancing an operating frequency and improving reliability in a system using at least level sense type sequence circuits as a plurality of sequence circuits....
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