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9031544 Status switching method for mobile device  
A status switching method for a mobile device is disclosed. The status switching method includes receiving a first request for switching a radio function of the mobile device from a first status to...
9030242 Data output timing control circuit for semiconductor apparatus  
A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code...
9021293 Methods for operating a memory interface circuit including calibration for CAS latency compensation in a plurality of byte lanes  
A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface...
9008196 Updating interface settings for an interface  
A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface...
9007231 Synchronization of distributed measurements in a borehole  
A system and method to synchronize distributed measurements in a borehole are described. The system includes a plurality of wired segments coupled together by couplers and a plurality of nodes...
9003220 Switch for clock synchronization over a switched fabric  
Devices and methods for synchronizing devices over a switched fabric. A switch receives a request packet from a device, transmits a completion packet to the device, determines an in-switch delay,...
9001595 Data strobe enable circuitry  
An integrated circuit may include memory interface circuitry that is used to communicate with off-chip memory. The memory interface circuitry may include data strobe (DQS) enable circuitry that...
9003221 Skew compensation for a stacked die  
An embodiment for skew compensation for a stacked die is disclosed. For an embodiment of an apparatus, an interposer has a first and a second integrated circuit die coupled to the interposer. The...
8990607 Memory interface circuits including calibration for CAS latency compensation in a plurality of byte lanes  
A memory interface circuit for read operations is described. The circuit includes one or more controller circuits, one or more read data delay circuits for providing CAS latency compensation for...
8984320 Command paths, apparatuses and methods for providing a command to a data block  
Command paths, apparatuses, and methods for providing a command to a data block are described. In an example command path, a command receiver is configured to receive a command and a command buffer...
8984322 Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed  
A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality...
8977883 Time synchronization improvements for interoperable medical devices  
A computer-implemented method is presented for synchronizing time between two handheld medical devices that interoperate with each other. The method includes: determining a first time as measured...
8977881 Controller core time base synchronization  
A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt...
8971469 Serial data communication method and serial data communication device  
A master device and slave devices are connected with each other through an SDA and an SCL, and at least one of a serial communication data signal communicated through the SDA and a serial...
8966309 Distribution of an incrementing count value  
Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from a...
8959379 Thermal protection method for computer system and device thereof  
A thermal protection method for a computer system including at least a processor includes monitoring the temperature and loading of the processor via a system firmware in the computer system,...
8959378 Output timing control circuit and semiconductor apparatus using the same  
An output timing control circuit of a semiconductor apparatus includes a delay amount counter block configured to count a delay amount of an output reset pulse signal based on an external clock...
8959268 Information processing apparatus, serial communication system, method of initialization of communication therefor and serial communication apparatus  
The disclosure provides a technique of enabling to appropriately confirm the state of a partner apparatus in high-speed serial communication. An information processing apparatus includes a master...
8943262 Non-volatile memory device  
A non-volatile memory device includes a first bank including a plurality of first page buffers, a second bank including a plurality of second page buffers, and an address counter configured to...
8938636 Generating globally coherent timestamps  
The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types...
8924766 Analysing timing paths for circuits formed of standard cells  
A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing...
8917130 Semiconductor device including a delay locked loop circuit  
A method for initializing a delay locked loop having a delay circuit includes a plurality of serially connected delay elements and a counter circuit for selecting an output of one of the delay...
8909970 Information processing apparatus or information processing method which supplies a clock to an external device  
If data received by the an information processing apparatus from an external device is delayed by one cycle or more with respect to a clock of the information processing apparatus, the information...
8907711 Integrated circuit having latch circuits and using delay circuits to fetch data bits in synchronization with clock signals  
A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section...
8904192 Method for protecting a programmable cryptography circuit, and circuit protected by said method  
A programmable cryptography circuit includes memory-based cells defining the logic function of each cell, integrating a differential network capable of carrying out calculations on pairs of binary...
8904221 Arbitration circuitry for asynchronous memory accesses  
A data processing system comprises a processor operating according to a first clock signal and a memory operating according to a second clock signal. The data processing system causes the processor...
8886988 Method of calibrating signal skews in MIPI and related transmission system  
In calibration mode, a clock signal and a data signal are respectively transmitted via a clock lane and a data lane of an MIPI. A test clock signal is provided by adjusting the phase of the clock...
8886987 Data processing unit and a method of processing data  
A data processing unit has a time information provider for processing a clock or a strobe signal, configured to provide a digitized clock or strobe time information on the basis of the clock or...
8880927 Time synchronization method and system for multicore system  
A time synchronization method and system for a multi-core system are provided. The time synchronization method comprises: establishing at least one clock synchronization domain, and respectively...
8881233 Resource management via periodic distributed time  
Systems and methods for providing resource management in a distributed network are disclosed. A loose collection of devices in a network may not be aware of the power restrictions for other...
RE45223 Method of self-synchronization of configurable elements of a programmable module  
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.),...
8872557 Data output timing control circuit for semiconductor apparatus  
A data output timing control circuit for a semiconductor apparatus includes a phase adjustment unit. The phase adjustment unit is configured to shift a phase of a read command as large as a code...
8872566 ***WITHDRAWN PATENT AS PER THE LATEST USPTO WITHDRAWN LIST***
Integrated circuit having latch circuits and using delay circuits to fetch data bits in synchronization with clock signals
 
A semiconductor integrated circuit includes a delay circuit connected between a source of data bits and a data input terminal of a latch circuit. The delay circuit includes a first delay section...
8868960 Synchronous clock stop in a multi nodal computer system  
A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one...
8862925 Pseudo synchronous serial interface synchronization method  
Primary serial interface logic is synchronized by cycling through a plurality of delays upon power up of the serial interface until a synchronization bit pattern is located. A minimum delay and a...
8862153 Automated portable call collection unit  
An automated portable call collection unit (APCCU) may gather information used in testing the accuracy of a wireless mobile device locating system. A GPS ground truth detector may detect the...
8856410 Semiconductor memory apparatus  
A semiconductor memory apparatus includes a synchronized signal generation circuit, a serial-to-parallel data conversion unit and a data storage region. The synchronized signal generation unit...
8850258 Calibration for source-synchronous high frequency bus synchronization schemes  
Embodiments provide bus synchronization system including a source module, a plurality of destination modules, and a data alignment controller. The source module is configured to synchronize a...
8843794 Method, system and apparatus for evaluation of input/output buffer circuitry  
Techniques and mechanisms for evaluating I/O buffer circuits. In an embodiment, test rounds are performed for a device including the I/O buffer circuits, each of the test rounds comprising a...
8843778 Dynamically calibrated DDR memory controller  
A method for calibrating a DDR memory controller is described. The method provides an optimum delay for a core clock delay element to produce an optimum capture clock signal. The method issues a...
8839018 Programmable mechanism for optimizing a synchronous data bus  
An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first...
8826059 Apparatus and method for buffering data between memory controller and DRAM  
A apparatus is provided for buffering data between a memory controller and a DRAM. The apparatus includes a phase locked loop (PLL), a phase interpolator for aligning a phase of an output clock...
8826057 Multiple time domain synchronizer circuits  
A multiple time domain synchronizer includes a data pipeline containing a plurality of serially-connected delay elements therein. A latency selection circuit is provided, which has a plurality of...
RE45109 Method of self-synchronization of configurable elements of a programmable module  
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.),...
8826058 Delay tolerant asynchronous interface (DANI)  
A Delay-tolerant Asynchronous Interface (DANI) is typically used to make the clock domains for reusable silicon intellectual property (IP) cores completely independent of each other. In fact, a...
8819474 Active training of memory command timing  
Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively...
8799697 Operating system synchronization in loosely coupled multiprocessor system and chips  
Methods, systems and devices configured to add synchronization to the entry and exit from low power modes in asynchronous operating systems on a multiprocessor system. A synchronizing agent tracks...
8793525 Low-power source-synchronous signaling  
Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second...
8782460 Apparatus and method for delayed synchronous data reception  
An apparatus that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network and a synchronous receiver disposed within a receiving device. The resistor...
8781052 Physical layer channel synchronization method for high bit-rate cable transmissions  
A system and method are described to provide a next generation cable gateway/modem based on the DOCSIS standard with a scheme to synchronously combine channels in the physical layer to increase...