|
Match
|
Document |
Document Title |
|
|
8006094 |
Trustworthy timestamps and certifiable clocks using logs linked by cryptographic hashes
A method and apparatus for creating and/or using trustworthy timestamps and certifiable clocks using logs linked by cryptographic hashes. In one embodiment, the method comprises maintaining a...
|
|
|
8006115 |
Central processing unit with multiple clock zones and operating method
One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a power supply voltage within the clock...
|
|
|
8001410 |
Efficient clocking scheme for ultra high-speed systems
There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock...
|
|
|
8001409 |
Synchronization device and methods thereof
A device includes different clock domains. Each clock domain is synchronized to a different clock signal, and the data transfer between clock domains occurs through a FIFO memory. It is determined...
|
|
|
7996701 |
Automated clock relationship detection
Automated clock relationship detection may quickly and reliably detect a clock relationship with minimal latency while reducing problems due to metastability occurring at a solitary instant or...
|
|
|
7996699 |
System and method for synchronizing multiple media devices
Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a...
|
|
|
7996700 |
Media data synchronization in a wireless network
A method of keeping global time in a wireless network, the method includes reading a Time Synchronization Function (TSF) to provide an initial time base. An interconnected clock control circuit is...
|
|
|
7995619 |
Methods and arrangements to model an asynchronous interface
Methods and arrangements to model an asynchronous interface are disclosed. Embodiments include transformations, code, state machines or other logic to generate a skew pattern for a semi-static or...
|
|
|
7996702 |
System and method for testing overclocking capability of CPU
A test system for overclocking capability of a central processing unit (CPU) includes a basic input and output system (BIOS), a frequency generator, and a watchdog timer. The BIOS includes an input...
|
|
|
7992177 |
Point-to-multipoint high definition multimedia transmitter and receiver
A high definition video transmitter and receiver are disclosed. The transmitter provides high definition video to a one-point receiver or to multipoint receivers. The transmission network is...
|
|
|
7987382 |
Method and apparatus for minimizing the influence of a digital sub-circuit on at least partially digital circuits
One inventive aspect relates to a digital sub-circuit suitable for embedding in an at least partially digital circuit for minimizing the influence of another digital sub-circuit on the at least...
|
|
|
7987381 |
Cyclemaster synchronization in a distributed bridge
A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon...
|
|
|
7986781 |
Method for controlling access to encrypted data
The invention concerns a method for controlling access to encrypted data (CT) by control words (CW), said control words being received by a security module in control messages (ECM) and returned to...
|
|
|
7983374 |
Methods and systems for providing variable clock rates and data rates for a SERDES
A method and apparatus for varying an output clock signal frequency to match the frequency of an output data signal frequency for a SERDES circuit while maintaining a constant input clock frequency...
|
|
|
7984319 |
Memory bus shared system
The invention reduces the pin terminal number of a controller that in parallel or simultaneously accesses a synchronous memory and an asynchronous memory. When a column address is latched to an...
|
|
|
7983115 |
System and method for managing time in automatic control equipment
A time management system that includes a first clock having a first counter operating on a first timebase, a second clock having a second counter operating on a second timebase identical to the...
|
|
|
7979732 |
Efficient utilization of a multi-source network of control logic to achieve timing closure in a clocked logic circuit
A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis...
|
|
|
7979730 |
Method and device for synchronizing cycle time of a plurality of TTCAN buses based on determined global time deviations and a corresponding bus system
A method, a device, and a bus system for synchronizing at least two TTCAN buses having at least one bus user, there being cycle times of the basic cycles in the TTCAN buses, a global time being...
|
|
|
7973607 |
RTC circuit with time value adjustment
A technique involves the use of an electronic device having a real-time clock (RTC) circuit. In particular, the technique involves obtaining an RTC value from the RTC circuit. The RTC value is...
|
|
|
7975161 |
Reducing CPU and bus power when running in power-save modes
A processing system includes a bus and a processor whose core is constrained to have one or more core clock signal frequencies no lower than a predetermined multiple of the lowest of one or more...
|
|
|
7971087 |
Dynamic clock control circuit and method
A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level of...
|
|
|
7970566 |
Correlating power consumption with CPU activity
Two or more sets of measurement data can be independently collected from causally related characteristics or elements. Such measurements can be synchronized with one another through the...
|
|
|
7966512 |
Data processing device and mobile device
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
|
|
|
7966468 |
Apparatus, system, and method for fast read request transfer through clock domains
A speculative transfer mechanism transfers a source synchronous read request from a first clock domain to a second clock domain. The address portion having address information is transferred to the...
|
|
|
7958355 |
Keytote component
Systems and methods that facilitate introducing devices having digital characteristics to one another, to mitigate a man-in-the-middle attack. A keytote component supplies initial session keys for...
|
|
|
7958382 |
Latency signal generator and method thereof
A latency signal generator and method thereof are provided. The example latency signal generator may include a sampling clock signal generator adjusting a plurality of initial sampling clock...
|
|
|
7954001 |
Nibble de-skew method, apparatus, and system
De-skew is performed on a nibble-by-nibble basis where a nibble is not limited to four bits.
|
|
|
7954153 |
Secured coprocessor comprising an event detection circuit
A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of...
|
|
|
7949080 |
Phase adjusting function evaluating method, transmission margin measuring method, information processing apparatus and computer readable information recording medium
A phase amount added to a clock signal or a plurality of data signals for adjusting a phase relationship therebetween in a reception apparatus is changed, and, a result of the phase adjusting...
|
|
|
7949120 |
Information processing system in which information expressing a current time point is transmitted from one computer to another for use in calculating an amount of delay in transferring data between the computers
In a system in which a first computer transmits data to a second computer, the first computer transmits data conveying time information to the second computer, with the information expressing a...
|
|
|
7949890 |
Method and system for precise synchronization of audio and video streams during a distributed communication session with multiple participants
Described are the architecture of such a system, algorithms for time synchronization during a multiway conferencing session, methods to fight with network imperfections such as jitter to improve...
|
|
|
7945800 |
Synchronization devices having input/output delay model tuning elements in signal paths to provide tuning capabilities to offset signal mismatch
Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such...
|
|
|
7945799 |
HVAC synchronization
Systems and methods are described for synchronizing an HVAC control system. A method, includes: a synchronization sequence including: reading a base time from an internal clock at a first time and...
|
|
|
7945804 |
Methods and systems for digitally controlled multi-frequency clocking of multi-core processors
A method and system for digitally controlled multi-frequency clocking are provided. The method includes receiving a system reference oscillator clock frequency at a microprocessor including...
|
|
|
7941684 |
Synchronization of processor time stamp counters to master counter
In one embodiment, an apparatus comprises one or more processors and a controller coupled to the processors. Each processor comprises at least one processor time stamp counter (TSC) and a first...
|
|
|
7940801 |
Method and apparatus for synchronizing digital video using a beacon packet
A WLAN compliant device which comprises a VCX), a MAC, a decoder which outputs video wherein said device compares time stamps to obtain a difference.
|
|
|
7940874 |
Receiver with adaptive strobe offset adjustment
Receiver for receiving a data stream via a data bus, which receiver samples the bits of the data stream in an over-sampling process, in which n bit strobe offsets are used and n data sets with i...
|
|
|
7937232 |
Data timestamp management
Embodiments of the present invention relate to managing timestamps associated with received data. According to one embodiment, data is collected from a device that generates data at a specified...
|
|
|
7937607 |
Asynchronous data holding circuit
An asynchronous data holding circuit including a source synchronizer which acquires an enable signal synchronized with a destination clock, in response to a rising or falling edge of the enable...
|
|
|
7937604 |
Method for generating a skew schedule for a clock distribution network containing gating elements
A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock...
|
|
|
7937605 |
Method of deskewing a differential signal and a system and circuit therefor
A high-definition multimedia interface (HDMI) receiver recovers high speed encoded data which are transmitted differentially over data channels of a lossy cable, along with a clock. Inter symbol...
|
|
|
7937608 |
Clock generating circuit and digital circuit system incorporating the same
A digital circuit system includes: a register, for receiving and registering digital data; an operation unit, for operating and generating resulting data according to the digital data registered in...
|
|
|
7934112 |
Rate verification of an incoming serial alignment sequence
A technique for rate verification of an incoming serial alignment sequence includes receiving an incoming serial stream. A determination is then made as to whether an align sequence is recognized...
|
|
|
7934265 |
Secured coprocessor comprising means for preventing access to a unit of the coprocessor
The present invention relates to a coprocessor comprising a calculation unit for executing a command, and a securization device for monitoring the execution of the command and supplying an error...
|
|
|
7933666 |
Adjustable data collection rate for embedded historians
Systems and methods that can vary a data collection rate via a rate adjustment component, to collect data with different level of granularity. The rate adjustment component can further include an...
|
|
|
7929361 |
Circuit using a shared delay locked loop (DLL) and method therefor
A transceiver (222) includes a receive circuit (320), a transmit circuit (340), a shared delay locked loop (DLL) (360), and a controller (210). The receive circuit (320) has a first input coupled...
|
|
|
7928770 |
I/O block for high performance memory interfaces
I/O blocks include input, output, and output enable circuits for interfacing with memory devices. The input circuit includes registers for capturing a double data rate signal, converting it into...
|
|
|
7930581 |
Automation device
The invention relates to an automation device, with which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The...
|
|
|
7926096 |
Enforcing time-based transaction policies on devices lacking independent clocks
A system and a method for operating a device that is not capable of independently maintaining a local time clock to enforce a time-based transaction policy that requires a reliable time reference....
|
|
|
7925912 |
Method and apparatus for fine edge control on integrated circuit outputs
A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more...
|