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8397098 Method for countervailing clock skew and core logic circuit using the same  
A method for countervailing clock skew between a first clock signal and a second clock signal in a core logic circuit. The second clock signal is sampled based on the first clock signal in a...
8397094 Node-to-node synchronizing apparatus, node-to-node synchronizing method, and computer product  
A node-to-node synchronizing apparatus includes an information generating unit. Before receiving a synchronization request for synchronization, the information generating unit receives, from each...
8392741 Latency control circuit and semiconductor memory device including the same  
A latency control circuit includes a delay unit configured to delay an input signal for a delay corresponding to a phase difference between an external clock and an internal clock and generate a...
8392686 System and method for read synchronization of memory modules  
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to...
8392742 Cyclemaster synchronization in a distributed bridge  
A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon...
8392746 Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof  
The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that...
8392739 Multi-core processor, its frequency conversion device and a method of data communication between the cores  
A multi-core processor and a frequency conversion device thereof as well as a method of communication between the cores are disclosed. Each processor core of the multi-core processor includes a...
8392740 Synchronization of converters having varying group-delays in a measurement system  
An analog-to-digital-converter (ADC) timing engine may simplify the use of Delta-Sigma ADCs by compensating for the group-delay of the ADC. The compensation may render the group-delay corresponding...
8391491 Communication system and synchronization control method  
A sender transmits to a receiver an optical signal that is phase-modulated in accordance with source data and a basis stored in a memory. The receiver phase-modulates the received optical signal in...
8386765 Method for the encrypted transmission of synchronization messages  
There is described a method for transmitting synchronization messages, for example PTP messages of the IEEE 1588 standard, the PTP message being inserted into a data packet in line with the...
8386827 Systems and methods for signal delay and alignment  
Various embodiments of the present invention provide systems and methods for event alignment control. For example, an event alignment control circuit is disclosed that includes a delay table, a...
8381010 Glitch-free clock switching circuit  
A circuit for switching clocks includes a first input intended to receive a first clock signal at a frequency alternately equal to a first value or a second value, a second input intended to...
8381008 Method and protection device for a power network accounting for route switching in a telecommunication network  
A protection device for a power network performs a method to align measuring times of first and second measurements of an electric quantity, taken at different ends of a power network line...
8375238 Memory system  
A memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with the second to Nth return read clocks. The memory controller takes in the Nth piece of data f...
8375237 Systems and methods for synchronization of an external control system with fieldbus devices  
Systems and methods for synchronization of an external control system with Fieldbus devices are described. A message including timing information for at least one Fieldbus device in direct or...
8375239 Clock control signal generation circuit, clock selector, and data processing device  
Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock...
8370676 Receiving apparatus and time correction method for receiving apparatus  
A receiving apparatus includes: a clock unit that outputs time information; a synchronizing (sync) packet receiving unit that receives a sync packet which contains transmitting time information and...
8370543 Busy detection logic for asynchronous communication port  
An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory...
8370124 High fidelity time domain for spacecraft emulation systems  
An emulation system includes a central time source generating a time reference and an emulated spacecraft control processor which contains an embedded processor that provides an emulated...
8370675 Precise clock synchronization  
A method for clock synchronization includes computing an offset value between a local clock time of a real-time clock circuit and a reference clock time, and loading the offset value into a...
8365005 Method and system for registering events in wind turbines of a wind power system  
Methods of registering events in a wind power system comprising at least two data processors. The data processors of said wind power system are mutually time synchronized. Events are registered in...
8365003 Synchronizing time domain signals in computing system using phase frequency slope value of cross power spectral density  
Some embodiments of the present invention provide a system that accurately synchronizes signals related to the operation of a computer system. During operation, the system receives a first...
8363773 Digital phase interpolation control for clock and data recovery circuit  
This invention discloses a phase interpolation controller for a clock and data recovery circuit receiving an indication of a phase relationship between a first and a second signal, the phase...
8365004 Configuring of intelligent electronic device  
The present disclosure provides a method, apparatus and configuration arrangement for configuring an intelligent electronic device, in which a group of function blocks defining at least a part of a...
8364290 Asynchronous control of machine motion  
A method of machine control can include providing at least a system master signal, selectively synchronizing at least sub-system master signal to the system master signal based on the value of the...
8362802 Asynchronous digital circuits including arbitration and routing primitives for asynchronous and mixed-timing networks  
Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and...
8359488 Keeping time in multi-processor virtualization environments  
A virtual machine receives a request for a current time. The virtual machine determines an approximation of the current time based on readings from one of a plurality of processors and compares the...
8359489 Frequency calibration circuit for automatically calibrating a frequency generated by an oscillator and method thereof  
A serial interface engine generates a series of digital data according to a pair of differential signals received from a high-speed Universal Serial Bus host and/or a full-speed universal serial...
8359481 Secured coprocessor comprising an event detection circuit  
A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of...
8358725 Synchronous sequential processing of multi-sampled phase  
The synchronous sequential processing of multi-sampled phase (SSP MSP) includes a method, a system and an apparatus for implementing programmable algorithms for analyzing and recovering data from a...
8356200 Negotiation between multiple processing units for switch mitigation  
A method for maintaining data and clock line synchronization, which may include a clock line that may be driven high after a clock line falling edge to mitigate a clock error. Additionally, the...
8356203 Asynchronous interface circuit and data transfer method  
An asynchronous interface circuit for transferring a data stream between different clock domains, the asynchronous interface circuits includes a data holding circuit for sequentially receiving and...
8352794 Control of clock gating  
Clock signal control circuitry is disclosed along with a method for switching a clock between modes and a computer program product. The clock signal control circuitry is for receiving a clock...
8350590 Method and apparatus for distributing clock signals  
A technique is provided that involves: configuring a clock generation circuit to output a first signal having a first frequency that is one of a plurality of frequencies that are different;...
8347133 Method for adjusting computer system and memory  
The invention provides an adjusting method of a system for changing a working frequency in an operation system for a computer system. The adjusting method includes establishing a look-up table, and...
8340295 High-speed cryptographic system using chaotic sequences  
A cryptographic system (500) that includes a data stream receiving device (502) configured for receiving a modified data stream representing data entries encrypted using a chaotic sequence of...
8341249 Synchronizing configuration information among multiple clients  
A user of multiple client devices (clients) makes application configuration changes on the clients from time to time. The configuration changes are stored in a local event log on each client, as...
8341450 Continuous timing calibrated memory interface  
A system that adjusts the timing of write operations at a memory controller is described. This system operates by observing timing drift for read data at the memory controller, and then adjusting...
8341454 Rendering a video stream based on digital clock generated based on timing information  
Systems, methods, and other embodiments associated with clock generation are provided. In one embodiment, a precise timing protocol message is parsed to extract timing information. Timing waveform...
8332680 Methods and systems for operating memory in two modes  
A memory system permits synchronized transmission of data with multiple memory modules in a dynamically expandable bus system such as with a point-to-point memory bus using strobed data...
8332683 Data processing system and image processing system  
A data processor comprising: a bus control circuit adapted to be interfaced with a synchronous DRAM which can be accessed in synchronism with a clock signal; a plurality of data processing modules...
8332681 Automatic reference frequency compensation  
In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method...
8327180 Data processing device and mobile device  
A microcomputer is provided having a memory card interface capable of correctly latching data even when a card such as an MMC card is connected thereto. In the microcomputer having an interface...
8321719 Efficient clocking scheme for a bidirectional data link  
A method for communication via a bidirectional data link between a processing device and a memory device. The memory device includes a clock source to generate a clock signal for driving a latching...
8320565 Method for generating downlink frame, and method for searching cell  
The present invention relates to a method of generating a downlink frame. The method of generating the downlink frame includes: generating a first short sequence and a second short sequence...
8316456 System and method for representing a secure time in a device based upon an insecure clock  
A system and method for providing modified rights information to an application on an electronic device. A centralized component monitors both a system clock and a secure clock. The centralized...
8316147 Time synchronization of multiple time-based data streams with independent clocks  
Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data...
8311211 Providing CPU smoothing of cryptographic function timings  
An approach that smoothes a cryptographic function's timing footprint is presented. A processor includes a “function timing smoother” that smoothes out spikes in the amount of time that a par...
8312309 Technique for promoting determinism among multiple clock domains  
A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit, In one embodiment, one or more execution units are placed in a deterministic state...
8307236 Oversampling-based scheme for synchronous interface communication  
In one embodiment, an apparatus to synchronously communicate on an interface that has an associated interface clock for a circuit that has an internal clock used internal to the circuit comprises a...