Sign up


Match Document Document Title
8185769 Method for ensuring synchronous presentation of additional data with audio data  
A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The...
8185773 Processor system employing a signal acquisition managing device and signal acquisition managing device  
A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state...
8176352 Clock domain data transfer device and methods thereof  
Two clock domains of a data processing device are each synchronized with a different clock signal. The clock signals are generated by clock generation logic. The clock generation logic also...
8176353 Method for the data transfer between at least two clock domains  
The invention describes a method for transferring data between a first clock domain having a first clock rate (CLK1) and at least one additional clock domain having a second clock rate (CLK2),...
8176351 Sampling mechanism for data acquisition counters  
One or more counter units of a data acquisition device used to perform sampling operations. Each of the counter units is configurable to operate in a selected one of a plurality of modes. During...
8170164 Transfer clocks for a multi-channel architecture  
A multi-channel architecture comprising a central facility that is under clock control of a central facility's clock signal, and a central transfer clock generator adapted for deriving a central...
8170067 Memory system with calibrated data communication  
A system includes a first integrated circuit device and a second integrated circuit device. The first device transmits a data sequence to the second integrated circuit device, and the second device...
8171334 Apparatus and method to interface two different clock domains  
A gearbox is placed between two clock domains to allow data to be transferred from one domain to the other. Although the two domains may operate at the same clock frequency, typically one domain...
8165296 Time of day encryption using TDMA timing  
Embodiments of the invention provide for encryption and decryption of data in a TDMA network using TDMA time values. In some embodiments, TDMA time values can be transmitted to terminals from a...
8166333 Network signal processing apparatus  
A network signal processing circuit includes a first signal processing module, a first sampling rate converter, a second signal processing module, a second sampling rate converter and a timing...
8166216 Floating frame timing circuits for network devices  
A networking device includes a network port configured to receive a message from a remote networking device. The network port includes a detector configured to detect reception of the message. A...
8161195 Adaptable management in sync engines  
Synchronization of two or more items can be optimized through the use of parallel execution of synchronization tasks and adaptable processing that monitors and adjusts for system loading. Two or...
8161212 Data operations across parallel non-volatile input/output devices  
An embodiment of a system for implementing parallel usage of a plurality of non-volatile input/output (I/O) devices can include an interface configured to receive, from a source, a source request...
8161314 Method and system for analog frequency clocking in processor cores  
A method of and system for frequency clocking in a processor core are disclosed. In this system, at least one processor core is provided, and that at least one processor core has a clocking...
8161302 Method and apparatus for data transmission in wireless local access network and system therefor  
An Apparatus, method, and system for transmitting data in a Wireless Local Access Network (WLAN) in a power management state are provided. The method includes registering a standby state entrance...
8155215 Transmission system, transmitter, receiver, and transmission method  
There is provided a circuit constituted by small-sized and simple logical gates which reduces the bit errors generated in a data sequence received by a receiver. A transmission system, in which a...
8151131 Signal synchronization method and signal synchronization circuit  
There is provided a signal synchronization method of performing signal synchronization between a device which operates in synchronization with a first clock signal and a processor which operates in...
8144872 System and method for generating analog-digital mixed chaotic signal, encryption communication method thereof  
A system and method for generating analog-digital mixed chaotic signal and an encryption communication method thereof are provided. In the system and method, the complementarity between continuous...
8145809 Busy detection logic for asynchronous communication port  
An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory...
8144689 Controlling asynchronous clock domains to perform synchronous operations  
A mechanism for controlling asynchronous clock domains to perform synchronous operations is provided. With the mechanism, when a synchronous operation is to be performed on a chip, the latches of...
8146078 Timer offsetting mechanism in a virtual machine environment  
In one embodiment, a method includes receiving a request to transition control to a virtual machine (VM) from a virtual machine monitor (VMM), calculating an offset value, receiving, during...
8145247 Clock synchronization for a wireless communications system  
Clock synchronization for a wireless communication system is described. The communication system utilizes a server with a radio coupled to receive a radio frequency (RF) signal and a clock...
8140882 Serial bus clock frequency calibration system and method thereof  
A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device and a second frequency calibration device both to...
8140925 Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan  
An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the...
8140881 Circuitry and method for detection of network node aging in communication networks  
The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a reset stage for resetting the network...
8135978 Performing a perform timing facility function instruction for sychronizing TOD clocks  
A system, method and computer program product for performing a Perform Timing Facility (PTFF) instruction for steering a Time of Day (TOD) clock of the computer system for synchronizing the TOD...
8135553 Method for clock calibration  
A method for clock calibration is provided. The method comprises receiving discontinuous reception period (DRX period) information from a base station, computing a calibration duration according to...
8134391 Semiconductor devices with signal synchronization circuits  
Semiconductor devices are disclosed providing synchronization circuits for synchronized signal distribution for a plurality of devices in a semiconductor device. The synchronization apparatus...
8135977 Process for digital, bidirectional data transmission  
The invention relates to a process for digital, bidirectional data transmission between a processing unit and a position encoder, as based on the transmission of frames of a predetermined bit...
8135975 Software programmable timing architecture  
A first output count is compared with first and second stored count values for generating an output event at a first node if the first Output count corresponds to the first or second stored count...
8130014 Network and method for setting a time-base of a node in the network  
A data communication network may, include a first sub-network and a second sub-network. The first sub-network may include two or more two master clocks, and a synchronization system connected to...
8132040 Channel-to-channel deskew systems and methods  
Systems and methods are disclosed herein to provide channel-to-channel skew control in accordance with one or more embodiments of the present invention. For example in accordance with an...
8132036 Reducing latency in data transfer between asynchronous clock domains  
A method and an interfacing circuit are disclosed for transmitting data between a first clock domain operating at a first clock frequency C1 and a second clock domain operating at a second clock...
8125930 Protocol for clock distribution and loop resolution  
Algorithms and data structure are described for constructing and maintaining a clock distribution tree (“CDT”) for timing loop avoidance. The CDT algorithms and data structure allows a node to mak...
8127170 Method and apparatus for audio receiver clock synchronization  
An audio receiver's output clock is synchronized based on a number of input and output audio samples measured over a predetermined sample period. In one embodiment, a sample difference may be...
8127152 Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode  
Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory...
8127169 Semiconductor memory device and method for generating internal control signal  
A semiconductor memory device includes: a command input unit configured to receive a plurality of external commands in synchronization with a rising edge of an internal clock to generate a...
8127171 Method for generating a clock signal  
An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock...
8126100 Communication protocol methods  
Communication protocol methods for performing signal synchronization, data transmission, and data acknowledgement between a transmitting device and a receiving device are provided. The methods are...
8121242 Frequency lock stability in device using overlapping VCO bands  
A system and method are provided for frequency lock stability in a receiver using overlapping voltage controlled oscillator (VCO) bands. An input communication signal is accepted and an initial VCO...
8122275 Write-leveling implementation in programmable logic devices  
Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by...
8122274 Method, system and computer program product for certifying a timestamp of a data processing system  
The disclosed embodiments present a system, method, and computer program product for certifying a timestamp generated by a data processing system. In some embodiments, the method includes receiving...
8122218 Semiconductor memory asynchronous pipeline  
An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous...
8122154 Storage system  
In a storage system that manages update prohibition (WORM) information, when time management is not performed with precision, there arises a possibility that an update prohibition (WORM) attribute...
8116354 Sync detection device and method for GNSS  
A sync detection device and method for a GNSS receiver. In modernized GNSS, each satellite transmits a data signal and a pilot signal. Correlations are performed between a data symbol stream...
8117330 Information processing device for relaying streaming data  
According to one embodiment, a method is described for relaying streaming data from a first external device and to transmit streaming data to a second external device. The method comprises (i)...
8117481 Apparatus and method for processing wirelessly communicated information within an electronic device  
An electronic device (12) for processing information wirelessly received from another electronic device (14) or to be wirelessly sent to the another electronic device (14) may include a first...
8112656 Clock distribution chip  
In one embodiment, a clock distribution chip includes a first clock input adapted to receive a first single-ended input clock signal, a second clock input adapted to receive a second single-ended...
8112754 Controlling body-bias voltage and clock frequency in a multiprocessor system for processing tasks  
In case of a task scheduling processing that assigns plural divided execution program tasks to plural processor units, a multiprocessor system using SOI/MOS transistors employs two processes; one...
8112655 Mesosynchronous data bus apparatus and method of data transmission  
A memory system is described, where the transmission time of data between memory modules is managed so that the overall time delay between specified points in the memory system is maintained a...