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8281177 Distributed control system  
There is provided a distributed control system including a plurality of field controllers which are connected through a control network. Each of the field controllers includes: a control clock that...
8281176 Buffer circuit and method  
The disclosed embodiments relate to buffer circuits and methods. One embodiment is a buffer circuit that receives a data signal, a first clock signal and a second clock signal, the buffer circuit...
8276014 Stalling synchronisation circuits in response to a late data signal  
A data processing circuitry for processing data is disclosed. The data processing circuitry comprises: a plurality of synchronization circuits for capturing and transmitting the data in response to...
8271821 Flexible RAM clock enable  
A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic...
8271823 DLL phase detection using advanced phase equalization  
A system and method are disclosed to generate and terminate clock shift modes during initialization of a synchronous circuit (e.g., a delay-locked loop or DLL). Upon initialization, the DLL is...
8271825 Synchronization devices having input/output delay model tuning elements in signal paths to provide tuning capabilities to offset signal mismatch  
Apparatus for synchronizing signals. For memory devices, such as SDRAMs, implementing a synchronization device to synchronize one signal, such as an external clock signal with a second signal, such...
8271824 Memory interface and operating method of memory interface  
A memory interface circuit includes a clock signal supply buffer configured to send a system clock signal which is supplied through a reference node, to a memory through a transmission line; a data...
8271822 Interactive device with time synchronization capability  
An interactive device having time synchronization capability is provided. In one embodiment, the interactive device has a computer processor that stores an internal clock. The computer processor...
8265921 Systems and methods for concurrently emulating multiple channel impairments  
Systems and methods are provided for concurrently emulating multiple channel impairments. The systems and methods may include storing a plurality of channel impairment profiles, where each channel...
8266466 Globally synchronized timestamp value counter  
The present invention relates to a synchronized timestamp mechanism in a packet processing system. This synchronized timestamp mechanism provides a globally synchronized counter value so counters...
8266405 Memory interface configurable for asynchronous and synchronous operation and for accessing storage from any clock domain  
An improved memory interface circuit is provided for accessing a storage array in one of two available modes, including a synchronous mode and an asynchronous mode. The improved memory interface...
8261120 Clock integrated circuit  
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more...
8259935 Secure communication method and system  
In a secure communication system, a first communication device includes a first list of numbers and a first number selector for periodically selecting a different number in the first list. The...
8261119 Test apparatus for testing device has synchronization module which synchronizes analog test module to digital test module based on synchronization signal received from digital test module  
There is provided a test apparatus for testing a device under test, including a plurality of test modules that test the device under test, and a synchronization module that is connected to each of...
8261121 Command latency reduction and command bandwidth maintenance in a memory circuit  
A method includes operating an arbitration logic of a memory controller at a core clock frequency lower than that of a memory clock frequency. The memory controller is configured to generate a...
8255733 Clock delay and skew control systems and methods  
A method of providing a clock signal for an embodiment includes performing a calibration for a closed loop control system to determine a control signal value that provides a desired tuning of the...
8255732 Self-stabilizing byzantine-fault-tolerant clock synchronization system and method  
Systems and methods for rapid Byzantine-fault-tolerant self-stabilizing clock synchronization are provided. The systems and methods are based on a protocol comprising a state machine and a set of...
8250398 Event time management in an electric vehicle charging station without a battery-backed real time clock  
An electric vehicle charging station, which does not include a battery-backed Real Time Clock, is in a charging station network managed by a charging station network server. Upon booting, the...
8245071 Method and apparatus of processing data independently and synchronizing and outputting processed data  
Provided are a method and apparatus for controlling a plurality of data processing modules that process data independently and output the processed data. A method of controlling a first data...
8245072 Signal transmission system and control method therefore  
A signal transmission system includes a transmitting device and a receiving device. The transmitting device includes a superimposition portion that superimposes at least one synchronizing signal on...
8245073 Method and apparatus synchronizing integrated circuit clocks  
Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin...
8245074 Clock integrated circuit  
The clock circuit of an integrated circuit operates with variations such as temperature, ground noise, and power noise. Various aspects of an improved clock integrated circuit address one or more...
8238379 Automation device  
The invention relates to an automation device, with which a multiplicity of physically distributed functional units communicate with each other by means of a common transmission protocol. The...
8234514 Method and apparatus for resolving clock management issues in emulation involving both interpreted and translated code  
Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is emulated to...
8228747 Delay adjustment device, semiconductor device and delay adjustment method  
Provided is a delay adjustment device that contributes to downsizing the circuit that adjusts a flight time. The delay adjustment device is connected to a memory, and adjusts a timing to retrieve...
8225252 Systems, methods, apparatus and computer readable mediums for use in association with systems having interference  
In some embodiments, a method includes characterizing a plurality of channels, each of the plurality of channels being a channel between a location and a respective one of the plurality of...
8223106 Display device and driving method thereof  
A driving circuit for a display device includes an input signal generator generating an input signal having one of a plurality of input frequencies corresponding to a respective one of a plurality...
8223910 Method and device for frame synchronization  
A device and a method for frame synchronization, the method includes providing a high frequency clock signal over a clock line during a transmission of information over a data line connected to a...
8225127 Method and system for precise synchronization of audio and video streams during a distributed communication session with multiple participants  
Described are the architecture of such a system, algorithms for time synchronization during a multiway conferencing session, methods to fight with network imperfections such as jitter to improve...
8225128 Electronic timer system, time control and generation of timing signals  
An electronic timer system includes a counter-based time generator (10) for continuously generating raw base time, and a translator (20) for translating between raw base time and local precise time...
8219846 Circuit for and method of receiving video data  
A circuit of an integrated circuit for receiving video data having a plurality of data streams of pixel data and a pixel clock is disclosed. The circuit comprises a plurality of data recovery...
8219844 Methods and systems for emulating a synchronous clear port  
A synchronous clear emulation circuit is provided. The synchronous clear emulation circuit includes a register having an asynchronous clear port. Moreover, the synchronous clear emulation circuit...
8218605 Preamble for synchronization  
A method for generating a preamble signal for a wireless communication system including the step of combining a plurality of different short PN sequences into a long PN sequence, wherein one of the...
8214618 Memory management method, medium, and apparatus based on access time in multi-core system  
A memory management method and apparatus based on an access time in a multi-core system. In the memory management method of the multi-core system, it is easy to estimate the execution time of a...
8214682 Synchronizing signals related to the operation of a computer system  
Some embodiments of the present invention provide a system that synchronizes signals related to the operation of a computer system. During operation, a set of correlation coefficients between a...
8209560 Transmission system where a first device generates information for controlling transmission and latch timing for a second device  
To provide a semiconductor device including a data input circuit and a data output circuit connected to a plurality of data input/output terminals, where at least one of the data input circuit and...
8207976 Circuit  
An embodiment of a circuit includes an output buffer, a data interface which is at least in a position to transmit data, the data interface being coupled to an output of the output buffer, a...
8209562 Double data rate converter circuit includes a delay locked loop for providing the plurality of clock phase signals  
In a memory interface, a delay locked loop (DLL) is added to the system in order to provide an accurate, PVT insensitive translation of the drive clocks into the write data eye. Adding a...
8208594 Method and device for clock-data recovery  
A method for the recovery of a clock signal from a data signal is provided where the edges of the signals are each represented as a chronologically-ordered sequence of timing points. In one...
8205111 Communicating via an in-die interconnect  
In one embodiment, the present invention includes a method for writing data from a writer coupled to a reader via an in-die interconnect into a queue entry according to a first clock of the writer,...
8201011 Timing optimization for paths in a processor  
A system and method for efficient timing optimization for asymmetric paths to replicated units. A microprocessor may include multiple instantiations of a processing core. Chip-level interconnects...
8201010 Automatic reference frequency compensation  
In a first embodiment of the present invention, a method for operating a device having a device reference clock, in a system including a host with a host reference clock is provided, the method...
8200873 Editing system, computer, timing notice apparatus, computer program, and method for acquiring timing  
An editing system in which a personal computer is easily configured as an editing apparatus that performs editing processing in synchronization with predetermined timing. According to the...
8194264 Method and apparatus for printing using synchronization signal  
A method and apparatus for printing using a synchronization signal are provided. Printing processes are performed in the apparatus by determining points in time for performing the printing...
8195954 Smart cards including separate clocks for key processing and non-volatile memory interface communications and methods of operating the same  
A memory controller for a smart card including a non-volatile memory can include an internal circuit that is configured to perform cryptographic key processing responsive to a first clock and a...
8195972 Jitter precorrection filter in time-average-frequency clocked systems  
Synchronous circuitry for processing digital data in which the data are filtered to compensate for expected jitter in time-average frequency clock signals. Time-average frequency synthesis...
8190944 Device configured to switch a clock speed for multiple links running at different clock speeds and method for switching the clock speed  
A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality...
8190941 Field control system  
The field control system includes: a field device; a field controller which is connected to a control network and which executes a computation processing for controlling the field device according...
8190942 Method and system for distributing a global timebase within a system-on-chip having multiple clock domains  
A global timebase system and method for a system-on-chip synchronizes multiple clock domains in each of a plurality of receiver modules by broadcasting a global timebase count value as Gray code...
8190722 Synchronization of timestamps to compensate for communication latency between devices  
Protocol analyzer systems enable synchronization of timestamps and the capture of data across serially chained boxes that are used together to monitor and capture network data. Through experiment,...