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8423812 Time correction in a semiconductor device using correction information provided by an adjacent semiconductor device  
In an information processing apparatus that includes a first and second semiconductor devices that are connected to each other and also includes a system control device that is connected to the...
8417982 Dual clock first-in first-out (FIFO) memory system  
Some of the embodiments of the present disclosure provide a method for operating a first in first out (FIFO) memory system in different clock domains, the method comprising receiving a write...
8417981 Time format conversion method, device and system  
A method and device for converting between different time domains at a local unit utilizing an processor is disclosed. Time counters to count time in at least two different formats are located...
8412974 Global synchronization of parallel processors using clock pulse width modulation  
A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter....
8412975 USB based synchronization and timing system  
A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure...
8411703 Method and apparatus for a reduced lane-lane skew, low-latency transmission system  
A method and apparatus for a multiple lane transmission system that provides a fixed, low-latency mode of operation with reduced lane-lane skew while process, voltage, and temperature (PVT)...
8412946 Trustworthy timestamps and certifiable clocks using logs linked by cryptographic hashes  
A method and apparatus for creating and/or using trustworthy timestamps and certifiable clocks using logs linked by cryptographic hashes. In one embodiment, the method comprises maintaining a...
8407513 Clock distribution with forward frequency error information  
This disclosure relates to providing an information signal to one or more sub-systems within a wireless communications device, where the information signal enables the sub-systems to operate based...
8407510 DDR interface bus control  
Systems and techniques for improved bus control, which may be particularly useful for double data rate (DDR) data transfer. A circuit may include a clock transmitter in communication with a clock...
8407508 Serial bus clock frequency calibration system and method thereof  
A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a...
8401359 Video receiving apparatus and video receiving method  
A video receiving apparatus having an input terminal to receive pixel-based video data transmitted with pixel clock synchronized with the video data is provided. The video receiving apparatus may...
8402300 Synchronization of clocks in autonomous components of an MR system and synchronous execution of commands in those components  
In a device and a method to execute commands in components of an imaging system, in particular of a magnetic resonance tomography system, local clocks in the components are temporally synchronized,...
8402303 Method for encoder frequency shift compensation  
The embodiments disclose a method for encoder frequency-shift compensation, including, determining frequency values of an input encoder signal, analyzing an encoder index clock signal and the input...
8402302 Timer system for maintaining the accuracy of a real time clock when synchronization source is not available  
An electronic timer system includes a counter-based time generator for continuously generating raw base time, and a translator for translating between raw base time and local precise time. The...
8402298 Array-type processor having delay adjusting circuit for adjusting a clock cycle in accordance with a critical path delay of the data path  
Disclosed is an array-type processor including a data path unit in which a plurality of processor elements are arranged in an array; a state-transition management unit that stores information for...
8402301 Delaying one-shot signal objects  
A device may include a processor to execute a thread. The processor may be further configured to execute a set of wrappers that are called from within the thread to invoke a set of one-shot signal...
8402299 Electronics device having timekeeping function and computer-readable record medium storing program for timekeeping function  
An electronics device comprising a time information acquisition unit which acquires time information representing present time from an external device, an update unit which updates reference time...
8397099 Using pulses to control work ingress  
The present invention extends to methods, systems, and computer program products for using pulses to control work ingress. Generally, embodiments of the invention use a variable-speed clock for...
8397095 Method and apparatus for synchronizing time of day of terminal in convergent network  
Provided is a method and apparatus for synchronizing a time of day (TOD) in a convergent network, wherein the TOD is received from a time server connected in the convergent network and is provided...
8396587 Conveyance control system and conveyance control method  
Provided is a conveyance control system in which fast and smooth control is realized without causing a control delay by a processing delay of a control apparatus such as a PLC, and wiring between a...
8397098 Method for countervailing clock skew and core logic circuit using the same  
A method for countervailing clock skew between a first clock signal and a second clock signal in a core logic circuit. The second clock signal is sampled based on the first clock signal in a...
8397094 Node-to-node synchronizing apparatus, node-to-node synchronizing method, and computer product  
A node-to-node synchronizing apparatus includes an information generating unit. Before receiving a synchronization request for synchronization, the information generating unit receives, from each...
8392741 Latency control circuit and semiconductor memory device including the same  
A latency control circuit includes a delay unit configured to delay an input signal for a delay corresponding to a phase difference between an external clock and an internal clock and generate a...
8392686 System and method for read synchronization of memory modules  
A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to...
8392742 Cyclemaster synchronization in a distributed bridge  
A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon...
8392746 Clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof  
The present invention provides a clock ratio controller for dynamic voltage and frequency scaled digital systems, and applications thereof. In an embodiment, a digital system is provided that...
8392739 Multi-core processor, its frequency conversion device and a method of data communication between the cores  
A multi-core processor and a frequency conversion device thereof as well as a method of communication between the cores are disclosed. Each processor core of the multi-core processor includes a...
8392740 Synchronization of converters having varying group-delays in a measurement system  
An analog-to-digital-converter (ADC) timing engine may simplify the use of Delta-Sigma ADCs by compensating for the group-delay of the ADC. The compensation may render the group-delay corresponding...
8391491 Communication system and synchronization control method  
A sender transmits to a receiver an optical signal that is phase-modulated in accordance with source data and a basis stored in a memory. The receiver phase-modulates the received optical signal in...
8386765 Method for the encrypted transmission of synchronization messages  
There is described a method for transmitting synchronization messages, for example PTP messages of the IEEE 1588 standard, the PTP message being inserted into a data packet in line with the...
8386827 Systems and methods for signal delay and alignment  
Various embodiments of the present invention provide systems and methods for event alignment control. For example, an event alignment control circuit is disclosed that includes a delay table, a...
8381010 Glitch-free clock switching circuit  
A circuit for switching clocks includes a first input intended to receive a first clock signal at a frequency alternately equal to a first value or a second value, a second input intended to...
8381008 Method and protection device for a power network accounting for route switching in a telecommunication network  
A protection device for a power network performs a method to align measuring times of first and second measurements of an electric quantity, taken at different ends of a power network line...
8375238 Memory system  
A memory controller takes in the first to (N−1)th pieces of data respectively in synchronization with the second to Nth return read clocks. The memory controller takes in the Nth piece of data f...
8375237 Systems and methods for synchronization of an external control system with fieldbus devices  
Systems and methods for synchronization of an external control system with Fieldbus devices are described. A message including timing information for at least one Fieldbus device in direct or...
8375239 Clock control signal generation circuit, clock selector, and data processing device  
Provided are a technique for high-speed switching between clock signals different in frequency, and a clock-control-signal-generation circuit which serves to generate a control signal for clock...
8370676 Receiving apparatus and time correction method for receiving apparatus  
A receiving apparatus includes: a clock unit that outputs time information; a synchronizing (sync) packet receiving unit that receives a sync packet which contains transmitting time information and...
8370543 Busy detection logic for asynchronous communication port  
An embodiment of the present invention is directed to a system for synchronizing independent time domain information. The synchronization of the device resource access information allows a memory...
8370124 High fidelity time domain for spacecraft emulation systems  
An emulation system includes a central time source generating a time reference and an emulated spacecraft control processor which contains an embedded processor that provides an emulated...
8370675 Precise clock synchronization  
A method for clock synchronization includes computing an offset value between a local clock time of a real-time clock circuit and a reference clock time, and loading the offset value into a...
8365005 Method and system for registering events in wind turbines of a wind power system  
Methods of registering events in a wind power system comprising at least two data processors. The data processors of said wind power system are mutually time synchronized. Events are registered in...
8365003 Synchronizing time domain signals in computing system using phase frequency slope value of cross power spectral density  
Some embodiments of the present invention provide a system that accurately synchronizes signals related to the operation of a computer system. During operation, the system receives a first...
8363773 Digital phase interpolation control for clock and data recovery circuit  
This invention discloses a phase interpolation controller for a clock and data recovery circuit receiving an indication of a phase relationship between a first and a second signal, the phase...
8365004 Configuring of intelligent electronic device  
The present disclosure provides a method, apparatus and configuration arrangement for configuring an intelligent electronic device, in which a group of function blocks defining at least a part of a...
8364290 Asynchronous control of machine motion  
A method of machine control can include providing at least a system master signal, selectively synchronizing at least sub-system master signal to the system master signal based on the value of the...
8362802 Asynchronous digital circuits including arbitration and routing primitives for asynchronous and mixed-timing networks  
Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and...
8359488 Keeping time in multi-processor virtualization environments  
A virtual machine receives a request for a current time. The virtual machine determines an approximation of the current time based on readings from one of a plurality of processors and compares the...
8359489 Frequency calibration circuit for automatically calibrating a frequency generated by an oscillator and method thereof  
A serial interface engine generates a series of digital data according to a pair of differential signals received from a high-speed Universal Serial Bus host and/or a full-speed universal serial...
8359481 Secured coprocessor comprising an event detection circuit  
A coprocessor includes a calculation unit for executing at least one command, and a securization device. The securization device includes an error detection circuit for monitoring the execution of...
8358725 Synchronous sequential processing of multi-sampled phase  
The synchronous sequential processing of multi-sampled phase (SSP MSP) includes a method, a system and an apparatus for implementing programmable algorithms for analyzing and recovering data from a...