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8533515 Method and system for synchronizing multiple secure clocks using an average adjusted time of the secure clocks if the average adjusted time is within the limit intersection and using a substitute average adjusted time if the averaged adjusted time is outside the limit intersection  
A method for synchronizing secure clocks in a system without using any external clock, a system configured to perform the method, and a computer medium storing system code. Each secure clock is...
8533516 Low power radio controlled clock incorporating independent timing corrections  
A timekeeping device that tracks the time provided by a digital broadcast and the protocol of that broadcast, defined by its data frame structure and modulation scheme, are adapted to allow for...
8533522 Double data rate output circuit  
A synchronization circuit for re-synchronizing data from an input clock to an output clock is presented. The first transparent latch receives data synchronized to an input clock. A second...
8533503 Managing power consumption in a multicore processor  
A method and computer-usable medium including instructions for performing a method of managing power consumption in a multicore processor comprising a plurality of processor elements with at least...
8527804 Architecture and method for eliminating store buffers in a DSP/processor with multiple memory accesses  
A method and apparatus for controlling system access to a memory that includes receiving first and second instructions, and evaluating whether both instructions can architecturally complete. When...
8527802 Memory device data latency circuits and methods  
A memory device can include a data path that includes a first-in-first-out circuit (FIFO) to transfer data according to a latency between at least one memory cell array and signal connections of...
8522058 Computer system with power source control and power source control method  
A computer system with power source control and a power source control method are presented. The computer system at least includes a first storage unit and a second storage unit, and the first...
8521925 Method and communication system for determining the time of an event in an IO device  
A method and communication system that provide an inexpensive approach that enables the times of events that are detected in IO device to be determined in a higher-level controller. The...
8516290 Clocking scheme for bridge system  
Various techniques are provided for bridging interfaces, such as different interfaces for use with a host device. In one example, a system includes an asynchronous first interface adapted to...
8514098 Synchronization between devices  
The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis...
8516292 Method and apparatus for providing symmetrical output data for a double data rate DRAM  
An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a...
8516276 Apparatus and method for controlling power supplied to fixing unit  
An apparatus and method for controlling the power supplied to a fixing unit are provided. The apparatus includes a voltage detector detecting a voltage of input power supplied to heat at least one...
8516291 Information processing apparatus, data reception device and method of controlling the information processing apparatus  
A clock adjustment circuit delays a phase of a clock signal on the basis of a TAP value so as to output an adjusted clock signal. By synchronizing transmission data with the adjusted clock signal,...
8510587 Time synchronization system and server using a baseboard management controller acquiring time signals to record occurrence time of system logs before than host system  
A time synchronization system includes a host system, a BIOS module, a BMC module, and a RTC module. The BIOS module is embedded in the host system. The BMC module is connected with the BIOS module...
8504862 Device and method for preventing lost synchronization  
A method and device for preventing a defect in a CDR circuit from hindering synchronization between connection nodes and for preventing connection failures. The CDR circuit generates a...
8502581 Multi-phase digital phase-locked loop device for pixel clock reconstruction  
A reconstruction circuit for the pixel clock in digital display units receiving analog display data uses a multi-phase reference clock and an all digital PLL for clock generation and...
8504868 Computer system with synchronization/desynchronization controller  
A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a...
8504864 Data sensor coordination using time synchronization in a multi-bus controller area network system  
A method is provided for synchronizing time in an unsynchronized vehicle controller area network system. A master control unit receives a global time from a time synchronization source. The master...
8504788 Memory controller, system and method for read signal timing calibration  
A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory...
8499186 Clock generator and USB module  
A clock generator is provided. The clock generator includes a crystal oscillator, an inverter coupled to the crystal oscillator in parallel, a first circuit and a second circuit. The crystal...
8495407 Node apparatus mounted in vehicle and in-vehicle network system  
An in-vehicle network system includes plural electronic control units data-communicably connected via a network. The electronic control units include a master unit and a node apparatus composed of...
8495410 Sampling phase correcting host controller, semiconductor device and method  
One embodiment provides a host controller which performs a phase shift correction of a sampling clock when sampling a signal received, includes a phase shift judging section which judges whether or...
8495408 Synchronization method and device for real-time distributed system wherein each module sets an indicator to signal whether it is currently able to operate synchronously with other modules and resets the indicator at a unified synchronization end time  
In order to solve the technical problem that in the current real-time distributed systems such as multi-antenna MIMO system, the implementation of synchronization between distributed modules by...
8495409 Host controller, semiconductor device and method for setting sampling phase  
According to one embodiment, there is provided a host controller, which samples reception data in a VDS mode and an FDS mode, includes a VDS phase register which holds a phase shift amount in the...
RE44383 Method of self-synchronization of configurable elements of a programmable module  
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.),...
8490089 Guest timer facility to improve management in a virtualized processing system  
A method includes, in a virtualized processing system, generating a local value of a first counter. The local value is accessible while executing in a first mode of the virtualized processing...
8489776 Apparatus and method for synchronizing wireless devices  
An apparatus for synchronizing devices includes a central access point node configured to utilize a low latency protocol to transmit a series of synchronization messages to the devices, transmit...
8489902 Semiconductor integrated circuit  
A semiconductor integrated circuit includes: a plurality of chips configured to receive an external voltage. Each one of the chips detects a signal delay characteristic of the one of the chips to...
8484501 System for delay locked loop control that provides delay interval stabilization  
The delay locked loop (“DLL”) delay interval can be locked to stop the DLL from wasting power in unnecessarily switching to synchronize the device with the DLL is associated to the system clo...
RE44365 Method of self-synchronization of configurable elements of a programmable module  
A method of synchronizing and reconfiguring configurable elements in a programmable unit is provided. A unit has a two- or multi-dimensional, programmable cell architecture (e.g., DFP, DPGA, etc.),...
8484389 AV renderer peripheral with dual inerrupt lines for staggered interrupts  
An audio-video (AV) playback chain and rendering peripheral device 300 for generating two or more interrupts 306, 308 with a programmable delay 304 between them. Such are configured to prevent two...
8477896 Structure for window comparator circuit for clock data recovery from bipolar RZ data  
A clock-data recovery doubler circuit for digitally encoded communications signals is provided. A window comparator includes two thresholds. A clock output is created by the window comparator and...
8473770 Semiconductor device and data processing system  
There is provided a serial reception circuit that can suppress the occurrence of a bit error due to long-period jitter while suppressing the power consumption. A serial reception circuit for...
8472569 Fine symbol timing estimation  
Systems and methods for fine symbol timing estimation are disclosed herein. In one embodiment, a wireless receiver includes a differential detector, a correlator, a coarse symbol timing estimator,...
8473638 Method and apparatus for time and frequency transfer in communication networks  
A timing system for time synchronization between a time server and a time client over a packet network. The timing system includes a time server for generating current timestamp information and a...
8464087 Flash memory devices with high data transmission rates and memory systems including such flash memory devices  
A flash memory device includes a memory cell array, a clock signal input, an input for receiving a signal designating a writing operating mode, a plurality of data input/output pads, and a data...
8464089 Tracing apparatus and tracing system  
A tracing apparatus for tracing operational information that is output from a plurality of processing units in relation to data processing operations, the tracing apparatus comprising for each of...
8453003 Communication method  
A communication method is provided to reduce an overhead of inter-processor synchronization for a communication phase in collective communication and to speed up the collective communication. Each...
8442943 Data transfer and synchronization between mobile systems using change log  
A system and method for synchronizing devices which can couple to the Internet, or any network. In one aspect a system for synchronizing data between a first system and a second system is provided....
8443224 Apparatus and method for decoupling asynchronous clock domains  
A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent...
8443225 Method and apparatus synchronizing integrated circuit clocks  
Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin...
8438415 Performing a perform timing facility function instruction for synchronizing TOD clocks  
A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to...
8434138 One time password  
A token calculates a one time password by generating a HMAC-SHA-1 value based upon a key K and a counter value C, truncating the generated HMAC-SHA-1 value modulo 10^Digit, where Digit is the...
8423812 Time correction in a semiconductor device using correction information provided by an adjacent semiconductor device  
In an information processing apparatus that includes a first and second semiconductor devices that are connected to each other and also includes a system control device that is connected to the...
8417982 Dual clock first-in first-out (FIFO) memory system  
Some of the embodiments of the present disclosure provide a method for operating a first in first out (FIFO) memory system in different clock domains, the method comprising receiving a write...
8417981 Time format conversion method, device and system  
A method and device for converting between different time domains at a local unit utilizing an processor is disclosed. Time counters to count time in at least two different formats are located...
8412974 Global synchronization of parallel processors using clock pulse width modulation  
A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter....
8412975 USB based synchronization and timing system  
A synchronization apparatus, comprising: a USB device having a USB microcontroller, circuitry for observing USB traffic, and circuitry for decoding from a USB data stream a periodic data structure...
8411703 Method and apparatus for a reduced lane-lane skew, low-latency transmission system  
A method and apparatus for a multiple lane transmission system that provides a fixed, low-latency mode of operation with reduced lane-lane skew while process, voltage, and temperature (PVT)...
8412946 Trustworthy timestamps and certifiable clocks using logs linked by cryptographic hashes  
A method and apparatus for creating and/or using trustworthy timestamps and certifiable clocks using logs linked by cryptographic hashes. In one embodiment, the method comprises maintaining a...