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8724320 Fan system and electronic device  
A fan system includes a pulse signal generation portion and a plurality of fans. Each of the plurality of fans preferably includes a motor portion; an impeller arranged to be rotated by the motor...
8726064 Interconnection system  
An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths...
8726061 System and method for synchronizing multiple media devices  
Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a...
8719616 Method for encoder frequency-shift compensation  
A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a...
8713344 Methods and apparatus for clock signal synchronization in a configuration of series connected semiconductor devices  
A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous device,...
8706268 Asynchronous control of machine motion  
A method of machine control can include providing at least a system master signal, selectively synchronizing at least sub-system master signal to the system master signal based on the value of the...
8707001 Method and system for measuring memory access time using phase detector  
Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference...
8707080 Simple circular asynchronous clock domain crossing technique for digital data  
A clock domain crossing technique that uses a circular buffer toggled by clocks from the two domains with output metastability protection. The resulting output is a pair of enable signals that may...
8707077 Method and apparatus for time synchronisation in wireless networks  
A wireless media distribution system is provided comprising an access point (6) for broadcasting media and a plurality of stations (2) for reception and playback of media. Each station is...
8700943 Controlling time stamp counter (TSC) offsets for mulitple cores and threads  
In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC...
8700818 Packet based ID generation for serially interconnected devices  
Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory...
8694818 Control circuit and operating method thereof  
A control circuit includes a plurality of clock synchronization units configured to shift an input signal in response to clock signals which are inputted thereto, a selection output block...
8693596 Gain calibration for a Mueller-Muller type timing error detector  
Apparatus and methods calibrate and control detector gain in a Mueller-Muller timing detector. A main signal path includes a Mueller-Muller based timing error detector (MM TED). The main signal...
8689035 Communication system, communication interface, and synchronization method  
An interface board includes a synchronizer that synchronizes a first time that is a time of the interface board to a base time based on a master synchronization signal that is supplied by an...
8687799 Data processing circuit and control method therefor  
When an encryption processing circuit encrypts data, a current flows in the encryption processing circuit. A noise current generated by a noise generation circuit is superimposed on the current...
8683252 Method for ensuring synchronous presentation of additional data with audio data  
A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The...
8683190 Circuitry for active cable  
Circuits, methods, and apparatus that allow signals that are compliant with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention...
8677173 Method and circuit for trimming an internal oscillator of a USB device  
A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of...
8677170 Method for generating a clock signal  
An apparatus for generating a delayed clock signal. The apparatus is a computer system with a processor to which a memory device is coupled. The memory device has a delay clock generator that has a...
8675797 Real time processing supported by programmable control unit  
The real time processing supported by programmable control unit (RTP PCU) includes a method, a system and an apparatus for implementing programmable algorithms for analyzing a very wide range of...
8677169 Session redundancy using a replay model  
A mechanism for synchronizing states of components in a first routing engine to corresponding components in a second routing engine is provided. In order to reduce the amount of data required to...
8675666 Systems and methods for distributing GPS clock to communications device  
A method for synchronizing network elements to a global clock derived from the GPS clock acquired by a plurality of base stations. The global clock is distributed to controllers of various...
8671302 Method and apparatus for wireless clock regeneration  
Methods and systems for operating a wireless clock system for multimedia datastream transmission and display. Source clock frames are compared with a reference clock frames and the clock difference...
8671303 Write-leveling implementation in programmable logic devices  
Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated by...
8671305 Techniques for adjusting periodic signals based on data detection  
A circuit includes a phase detector circuit, a phase frequency detector circuit, a data detection circuit, a multiplexer circuit, and a clock signal generation circuit. The phase detector circuit...
8670137 Method and apparatus for printing using synchronization signal  
A method and apparatus for printing using a synchronization signal are provided. Printing processes are performed in the apparatus by determining points in time for performing the printing...
8671301 Method for ensuring synchronous presentation of additional data with audio data  
A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The...
8665738 Transmission apparatus and signal transmission method  
A transmission apparatus stores frame data of a first frame in a second frame having a bit rate different from that of the first frame through regulation of the amount of stuffs to be stored in the...
8667315 Synchronization control apparatus, information processing apparatus, and synchronization management method for managing synchronization between a first processor and a second processor  
A synchronization control apparatus includes a counter that carries out a counting and outputs resulting count information, a timeout time holder that holds a predetermined timeout time and outputs...
8666006 Systems and methods for high speed data recovery with free running sampling clock  
Systems and methods are disclosed for improving digital feed-forward data recovery of high speed data from a received data stream in a data transceiver or receiver where the receiver clock is...
8667316 Precision synchronisation architecture for superspeed universal serial bus devices  
A method of providing a synchronization channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB...
8661284 Method and system to improve the operations of a registered memory module  
A method and system to improve the operations of a registered memory module. In one embodiment of the invention, the registered memory module allows asynchronous read and write operations when a...
8650429 Clock phase alignment  
A method and apparatus for clock phase alignment are described. An external clock is aligned to an internal clock by adjusting phase of the external clock. The external clock is of a physical...
8645741 Method and system for predicting a latency spike category of audio and video streams to adjust a jitter buffer size accordingly  
Described are the architecture of such a system, algorithms for time synchronization during a multiway conferencing session, methods to fight with network imperfections such as jitter to improve...
8644439 Circuits and methods for signal transfer between different clock domains  
In certain embodiments, a circuit for transferring signals from a source clock domain to a destination clock domain comprises a first pulse generation circuit, a hold flip-flop circuit, a clocked...
8638251 Delay compensation for sigma delta modulator  
A continuous time delta-sigma modulator is provided that includes an integrator stage including a plurality of integrators; a quantizer to receive an input signal from the integrator stage and...
8631266 Semiconductor memory device and method of controlling the same  
A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal;...
8631267 Adjustable byte lane offset for memory module to reduce skew  
Disclosed herein are solutions for addressing the problem of skew of data within a byte lane by factors caused external to the integrated circuit or module providing the data. To compensate for...
8631265 Synchronization circuit that facilitates multiple parallel reads and writes  
The disclosed embodiments provide a synchronization circuit that supports multiple parallel reads and writes. This synchronization circuit includes multiple coupled data storage locations that...
8630317 Memory system with calibrated data communication  
An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical...
8627132 Autonomous multi-device event synchronization and sequencing technique eliminating master and slave assignments  
An apparatus and method for event synchronization. One or more devices that have a plurality of events to be carried out in a scheduled order in time are connected to a single shared time position...
8627133 Virtual machine boot speed-up by clock acceleration  
A mechanism for virtual machine (VM) boot speed-up by clock acceleration is disclosed. A method of the invention includes detecting that a VM managed by a hypervisor of a host machine is starting a...
8626980 High density, low jitter, synchronous USB expansion  
A method of providing high density expansion of a USB network, the method comprising: attaching a plurality of USB hubs to adjacent slots in a PXI instrumentation chassis; configuring one of the...
8626852 Email thread monitoring and automatic forwarding of related email messages  
A computer system can implement a mechanism for email thread monitoring and automatic forwarding of related email messages. In one embodiment, a first email message is provided from an email...
8621109 Adaptable management in sync engines  
Synchronization of two or more items can be optimized through the use of parallel execution of synchronization tasks and adaptable processing that monitors and adjusts for system loading. Two or...
8621076 Delivery performance analysis for internet services  
One preferred embodiment of the present invention provides systems and methods for analyzing the delivery performance of newsgroup services. Briefly described, in architecture, one embodiment,...
8621253 Processor boost based on user interface demand  
A method and system for boosting a clock frequency for a processor in a mobile device based on user interface (UI) demand are described. In response to a user interaction through a UI in the mobile...
8615673 Device synchronization using independent clocks  
At least one radio frequency (RF) instrument may be configured according to a plurality of RF measurement configurations for performing a plurality of tests on a device under test (DUT). A list of...
8613065 Method and system for multiple passcode generation  
This invention relates to a method and a system for generating user passcodes for each of a plurality of transaction providers from a mobile user device. A method and system for activating a...
8607089 Interface for storage device access over memory bus  
A nonvolatile storage or memory device is accessed over a memory bus. The memory bus has an electrical interface typically used for volatile memory devices. A controller coupled to the bus sends...