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8775852 Method for sensing input signal changes  
A method for sensing input signal changes at an input of an input/output module operated in an automation system in which a signal is sampled by an input/output module. A change event and a...
8775849 Systems and methods for transporting time-of-day information in a communication system  
Systems and methods for synchronizing a clock at a customer premises equipment (CPE) location with a master clock at a central office (CO) location are described. One embodiment is a method that...
8775850 Transferring state information between electronic devices  
Some embodiments enable a first electronic device (e.g., a notebook computer) to obtain state information directly from another electronic device (e.g., a smartphone) so that the first electronic...
8775853 Device and method for preventing lost synchronization  
A method for synchronizing two connection nodes by a reception node of the connection nodes with a clock data recovery circuit that generates a synchronization clock from input data. The method...
8775856 System and method for generating clock signal for a plurality of communication ports by selectively dividing a reference clock signal with a plurality of ratios  
Various techniques are provided to generate a plurality of reference clock signals using a single reference clock signal generator. In one example, a clock signal generation system includes a...
8769067 Systems and methods for statistics exchange between cores for load balancing  
Systems and methods for consolidating metrics and statistics used for load balancing by a plurality of cores of a multi-core intermediary are disclosed. A timer operating on each packet engine of...
8766667 Asynchronous digital circuits including arbitration and routing primatives for asynchronous and mixed-timing networks  
Asynchronous digital circuits are described, including arbitration and routing primitives for asynchronous and mixed-timing networks. An asynchronous arbitration primitive has two data inputs and...
8769330 Dynamic voltage and frequency scaling transition synchronization for embedded systems  
Methods and apparatuses are provided that allow for the synchronization of an operating point transition in an embedded system environment. Identification of an upcoming operating point...
8762762 Distributed synchronization and timing system for generating local clock signal based on a desired clock signal embedded in USB data stream  
A method and apparatus for controlling the phase and frequency of the local clock of a USB device, the apparatus comprising circuitry for observing USB traffic and decoding from the USB traffic a...
8761327 Rational clock divider for media timestamps and clock recovery functions  
Systems and methods are described including receiving a clock signal, using rational clock divider (RCD) logic to generate a lower frequency clock signal in response to the received clock signal,...
8756395 Controlling DRAM at time DRAM ready to receive command when exiting power down  
Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory...
8755308 Protocol for clock distribution and loop resolution  
In response to a network topology change, a clock root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to...
8756452 Using pulses to control work ingress  
Pulses are used to control work ingress. Generally, a variable-speed clock is used for accepting work for lower-priority services. A clock rate is controlled by a load monitor. The load monitor...
8756446 Microprocessor having a low-power mode and a non-low power mode, data processing system and computer program product  
A microprocessor has a low-power mode and a non-low power mode. The microprocessor includes a processor core for executing instructions provided to the microprocessor and a clock providing a clock...
8751852 Programmable mechanism for delayed synchronous data reception  
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a...
8751853 Quad-data rate controller and implementing method thereof  
A Quad-Data Rate (QDR) controller and an implementation method thereof are disclosed in the present invention. The controller includes: an arbiter, a control state machine, a read data sampling...
8751851 Programmable mechanism for synchronous strobe advance  
An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive...
8751850 Optimized synchronous data reception mechanism  
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The...
8745431 Compound universal serial bus architecture providing precision synchronisation to an external timebase  
A method of synchronizing a compound Super Speed USB device, comprising: providing data communication between a host computing device and the compound Super Speed USB device across the Super Speed...
8743633 Integrated semiconductor device  
An integrated semiconductor device including: a first semiconductor device having a clock generation section, first data storage sections storing input data as transfer data, data output terminals...
8745430 Clock synchronization across an interface with an intermittent clock signal  
The disclosed embodiments provide a system that facilitates synchronization between a first component and a second component connected to the first component via an interface in a computer system....
8732509 Timing synchronization circuit with loop counter  
An apparatus for synchronizing an output clock signal with an input clock signal includes a first timing synchronization circuit, control logic, and a counter. The first timing synchronization...
8732514 Using pulses to control work ingress  
Clock pulses of a variable speed clock are adjusted relative to system utilization. A load monitor periodically collects sensor measurements of resources and based on the sensor measurements, the...
8724663 Implementation method and system, main control device and smart card for information transmission  
An implementation method and system, main control device and smart card for information transmission are provided. The method includes: the smart card notifying the main control device of the...
8726062 Data recovery architecture (CDR) for low-voltage differential signaling (LVDS) video transceiver applications  
The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is...
8724320 Fan system and electronic device  
A fan system includes a pulse signal generation portion and a plurality of fans. Each of the plurality of fans preferably includes a motor portion; an impeller arranged to be rotated by the motor...
8726064 Interconnection system  
An interconnection system, apparatus and method is described for arranging elements in a network, which may be a data memory system, computing system or communications system where the data paths...
8726061 System and method for synchronizing multiple media devices  
Multiple media devices are synchronized in a multi-media system having a computer system, a plurality of media devices, and a display system. Each media device to be synchronized receives a...
8719616 Method for encoder frequency-shift compensation  
A method for encoder frequency-shift compensation includes determining frequency values of an input encoder signal, determining repeatable frequency-shifts of the frequency values and generating a...
8713344 Methods and apparatus for clock signal synchronization in a configuration of series connected semiconductor devices  
A system includes a system controller and a configuration of series-connected semiconductor devices. Such a device includes an input for receiving a clock signal originating from a previous...
8706268 Asynchronous control of machine motion  
A method of machine control can include providing at least a system master signal, selectively synchronizing at least sub-system master signal to the system master signal based on the value of the...
8707001 Method and system for measuring memory access time using phase detector  
Methods and systems for determining a memory access time are provided. A first phase skew is measured between a first clock signal used by a memory and a second clock signal used as a reference...
8707080 Simple circular asynchronous clock domain crossing technique for digital data  
A clock domain crossing technique that uses a circular buffer toggled by clocks from the two domains with output metastability protection. The resulting output is a pair of enable signals that may...
8707077 Method and apparatus for time synchronisation in wireless networks  
A wireless media distribution system is provided comprising an access point (6) for broadcasting media and a plurality of stations (2) for reception and playback of media. Each station is...
8700943 Controlling time stamp counter (TSC) offsets for mulitple cores and threads  
In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC...
8700818 Packet based ID generation for serially interconnected devices  
Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory...
8694818 Control circuit and operating method thereof  
A control circuit includes a plurality of clock synchronization units configured to shift an input signal in response to clock signals which are inputted thereto, a selection output block...
8693596 Gain calibration for a Mueller-Muller type timing error detector  
Apparatus and methods calibrate and control detector gain in a Mueller-Muller timing detector. A main signal path includes a Mueller-Muller based timing error detector (MM TED). The main signal...
8689035 Communication system, communication interface, and synchronization method  
An interface board includes a synchronizer that synchronizes a first time that is a time of the interface board to a base time based on a master synchronization signal that is supplied by an...
8687799 Data processing circuit and control method therefor  
When an encryption processing circuit encrypts data, a current flows in the encryption processing circuit. A noise current generated by a noise generation circuit is superimposed on the current...
8683252 Method for ensuring synchronous presentation of additional data with audio data  
A recording medium, method and apparatus for managing data are discussed. According to an embodiment, the present invention provides a method of reproducing main data and additional data. The...
8683190 Circuitry for active cable  
Circuits, methods, and apparatus that allow signals that are compliant with multiple standards to share a common connector on an electronic device. An exemplary embodiment of the present invention...
8677173 Method and circuit for trimming an internal oscillator of a USB device  
A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of...
8677170 Method for generating a clock signal  
An apparatus for generating a delayed clock signal. The apparatus is a computer system with a processor to which a memory device is coupled. The memory device has a delay clock generator that has...
8675797 Real time processing supported by programmable control unit  
The real time processing supported by programmable control unit (RTP PCU) includes a method, a system and an apparatus for implementing programmable algorithms for analyzing a very wide range of...
8677169 Session redundancy using a replay model  
A mechanism for synchronizing states of components in a first routing engine to corresponding components in a second routing engine is provided. In order to reduce the amount of data required to...
8675666 Systems and methods for distributing GPS clock to communications device  
A method for synchronizing network elements to a global clock derived from the GPS clock acquired by a plurality of base stations. The global clock is distributed to controllers of various...
8671302 Method and apparatus for wireless clock regeneration  
Methods and systems for operating a wireless clock system for multimedia datastream transmission and display. Source clock frames are compared with a reference clock frames and the clock...
8671303 Write-leveling implementation in programmable logic devices  
Circuits, methods, and apparatus for memory interfaces that compensate for skew between a clock signal and DQ/DQS signals that may be caused by a fly-by routing topology. The skew is compensated...
8671305 Techniques for adjusting periodic signals based on data detection  
A circuit includes a phase detector circuit, a phase frequency detector circuit, a data detection circuit, a multiplexer circuit, and a clock signal generation circuit. The phase detector circuit...