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7603492 Automatic generation of streaming data interface circuit  
A streaming data interface device ( 700 ) of a streaming processing system ( 200 ) is automatically generated by selecting a set of circuit parameters ( 610 ) consistent with a set of circuit...
7603488 Systems and methods for efficient memory management  
Systems and methods for providing efficient memory allocation, reduced processor intervention and power consumption, and increased memory access bandwidth. One embodiment comprises a system...
7500240 Apparatus and method for scheduling threads in multi-threading processors  
An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second...
7460989 Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU with a sequential language  
A method is provided, wherein a virtual internal master clock is used in connection with a RISC CPU. The RISC CPU comprises a number of concurrently operating function units, wherein each unit runs...
7451146 Almost non-blocking linked stack implementation  
A method and computer system for implementing, in a multithreaded environment, an almost non-blocking linked list allow a lock-free access provided that certain conditions are met. The approach...
7444488 Method and programmable unit for bit field shifting  
A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first...
7313788 Vectorization in a SIMdD DSP architecture  
A method for determining vectorization configurations in a computer processor architecture, the method including identifying a vectorizable loop in a computer program, identifying a memory access...
7293258 Data processor and method for using a data processor with debug circuit  
A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of...
7237086 Configuring a management module through a graphical user interface for use in a computer system  
A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the...
7206920 Min/max value validation by repeated parallel comparison of the value with multiple elements of a set of data elements  
A method of locating a target value includes loading the target value into elements of a first register. The first register includes N elements (N>0). The method also includes indicating in...
7197625 Alignment and ordering of vector elements for single instruction multiple data processing  
The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a...
7146486 SIMD processor with scalar arithmetic logic units  
A scalar processor that includes a plurality of scalar arithmetic logic units and a special function unit. Each scalar unit performs, in a different time interval, the same operation on a different...
7130985 Parallel processor executing an instruction specifying any location first operand register and group configuration in two dimensional register file  
Described herein is a data processor that comprises a register memory and a processor unit. The processor unit simultaneously executes a single instruction on a plurality of operands in the...
7062633 Conditional vector arithmetic method and conditional vector arithmetic unit  
It is decided whether a first source data from the memory 101 is a data which is to be subjected to arithmetic or not by a state flag detection means 150 , the result of the decision is retained...
7027446 Method and apparatus for set intersection rule matching  
A method and apparatus for of high-speed and memory efficient rule matching, the rule matching being performed on an m-dimensional universe with each dimension bound by a given range of coordinate...
6963341 Fast and flexible scan conversion and matrix transpose in a SIMD processor  
The present invention provides efficient ways to implement scan conversion and matrix transpose operations using vector multiplex operations in a SIMD processor. The present method provides a very...
6954841 Viterbi decoding for SIMD vector processors with indirect vector element access  
A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal...
6922716 Method and apparatus for vector processing  
A processor includes a first vector processing unit including a first register file and first vector arithmetic logic unit; a second vector processing unit including a second register file and...
6904510 Data processor having a respective multiplexer for each particular field  
A data processor that can perform instructions in parallel on respective fields in an operand includes a respective multiplexer for each of the respective fields. Each respective multiplexer is...
6782468 Shared memory type vector processing system, including a bus for transferring a vector processing instruction, and control method thereof  
A shared memory type vector processing system in which CPUs are connected by a bus for transferring a vector processing instruction generated from any of the CPUs to each of the CPUs, and the...
6560775 Branch preparation  
A method and system for preparing branch instruction of a computer program, for compiling and execution in a computer system, in which each transfer instruction is split into two instructions: a...
6504495 Clipping data values in a data processing system  
A clipping and quantization technique is described for producing clipped numbers in a range of 0 to Nāˆ’1 (from unclipped numbers in a range of āˆ’0.5N to (1.5Nāˆ’1)), where N is 2 m and m is the...
6446193 Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture  
A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second...
6401194 Execution unit for processing a data stream independently and in parallel  
A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic...
6336154 Method of operating a computer system by identifying source code computational elements in main memory  
A computer system comprises: a processing system for processing data; a memory for storing data processed by, or to be processed by, the processing system; a memory access controller for...
6327668 Determinism in a multiprocessor computer system and monitor and processor therefor  
A multiprocessor computer system which provides fault tolerance includes a number of processing sets. At least one of the processing sets is operable asynchronously of a second processing set. A...
6324638 Processor having vector processing capability and method for executing a vector instruction in a processor  
A processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the...
6314471 Techniques for an interrupt free operating system  
A method and system in a multithreaded processor for processing events without interrupt notifications. In one aspect of the present invention, an operating system creates a thread to execute on a...
6308250 Method and apparatus for processing a set of data values with plural processing units mask bits generated by other processing units  
A method and system for operating a computing system having multiple processing units. According to a new machine instruction, called the iota instruction, the computing system operates on a vector...
6269435 System and method for implementing conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector  
A processor implements conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a...
6249858 Information processing apparatus having a CPU and an auxiliary arithmetic unit for achieving high-speed operation  
An information processing apparatus such as a microcomputer consisting of a CPU and a coprocessor is provided. The CPU and the coprocessor are connected through a data bus and an address bus....
6237066 Supporting multiple outstanding requests to multiple targets in a pipelined memory system  
One embodiment of the present invention provides an apparatus that supports multiple outstanding load and/or store requests from an execution engine to multiple sources of data in a computer...
6209126 Stall detecting apparatus, stall detecting method, and medium containing stall detecting program  
A stall detecting apparatus and a stall detecting method reduce labor and time to develop a program. The apparatus has an input portion for reading a source program, an interpreter for interpreting...
6202141 Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectors  
A vector multiplication mechanism is provided that partitions vector multiplication operation into even and odd paths. In an odd path, odd data elements of first and second source vectors are...
6157994 Microprocessor employing and method of using a control bit vector storage for instruction execution  
A control bit vector storage is provided. The present control bit vector storage (preferably included within a functional unit) stores control bits indicative of a particular instruction. The...
6073158 System and method for processing multiple received signal sources  
A system and method for time slicing multiple received data streams utilizing multiple processors in such a manner as to ensure that all processors are running at full capability and are...
6061777 Apparatus and method for reducing the number of rename registers required in the operation of a processor  
One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently...
6061521 Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle  
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional...
6055558 Pacing of multiple producers when information is required in natural order  
A system and method for pacing, or controlling, the processing of multiple producers when a consumer requires results from the producers in natural order. This invention regulates the use of system...
6044448 Processor having multiple datapath instances  
A processor having a sliceable architecture wherein a slice is the minimum configuration of the processor datapath. The processor can instantiate multiple slices and each slice has a separate...
5996066 Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions  
An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized...
5991764 Data structure specifying differing fan-in tree and fan-out tree computation patterns supporting a generic reduction object for data parallelism  
A data structure supporting a data-parallel reduction operation performed by a group of threads, a rope, participating in a multi-level two-phase tree structure: a fan-in computation phase followed...
5963744 Method and apparatus for custom operations of a processor  
Custom operations are useable in processor systems for performing functions including multimedia functions. These custom operations enhance a system, such as PC system, to provide real-time...
5826095 Method and apparatus for maintaining the order of data items processed by parallel processors  
A data processing system includes two or more parallel processors, a distributor and a combiner. The processors process input data items and generate corresponding output data items. The...
5802391 Direct-access team/workgroup server shared by team/workgrouped computers without using a network operating system  
A system of computers having team/workgroup features built in. A typical hardware component thereof is a unitary chassis of a regular single IBM-PC tower-chassis footprint, designed to house...
5727229 Method and apparatus for moving data in a parallel processor  
A method and apparatus for moving data in a parallel processing system (3). In one embodiment, a single instruction accesses one significant bit of information from each element in processing...
5710914 Digital signal processing method and system implementing pipelined read and write operations  
A digital signal processing system and method for executing instructions with decode, read, execute, and write pipeline cycles. In the decode cycle, control signals are generated which determine...
5625834 Information processing section and system for operating a plurality of vector pipeline sets in two different modes  
In an information processing system of the present invention, a vector processor has a plurality of vector pipeline sets operable under control of an instruction controller. The vector pipeline...
5623685 Vector register validity indication to handle out-of-order element arrival for a vector computer with variable memory latency  
Method and apparatus for vector processing on a computer system. As the last element of a group of elements (called a "chunk") in a vector register is loaded from memory, the entire chunk is marked...
5598571 Data processor for conditionally modifying extension bits in response to data processing instruction execution  
A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single...
Matches 1 - 50 out of 79 1 2 >