Matches 1 - 42 out of 42
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7467138 Algorithm for sorting bit sequences in linear complexity  
A method and associated algorithm for in-place sorting S sequences of binary bits stored contiguously in an array within a memory device of a computer system prior to the sorting. Each sequence...
7460989 Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU with a sequential language  
A method is provided, wherein a virtual internal master clock is used in connection with a RISC CPU. The RISC CPU comprises a number of concurrently operating function units, wherein each unit runs...
7444488 Method and programmable unit for bit field shifting  
A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first...
7356710 Security message authentication control instruction  
A method, system and computer program product for computing a message authentication code for data in storage of a computing environment. An instruction specifies a unit of storage for which an...
7237086 Configuring a management module through a graphical user interface for use in a computer system  
A customization program for use in customizing a baseboard management controller used for monitoring operation of various computer system components is disclosed. A user interacts with the...
7231261 Method for automatically obtaining an operational sequence of processes and a tool for performing such method  
In order to automatically calculate an operational sequence of processes that determine an output value from at least one input value, a multitude of processes (P 1 –P 8 ), whose inputs are...
7100026 System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values  
A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output...
7000093 Cellular automaton processing microprocessor prefetching data in neighborhood buffer  
A cellular automaton cache memory architecture. On a micro-processor that is also capable of executing general-purpose instructions, a cache memory is provided to store instructions and data for...
6963341 Fast and flexible scan conversion and matrix transpose in a SIMD processor  
The present invention provides efficient ways to implement scan conversion and matrix transpose operations using vector multiplex operations in a SIMD processor. The present method provides a very...
6954927 Hardware supported software pipelined loop prologue optimization  
A method for optimizing a software pipelineable loop in a software code is provided. The loop comprises one or more pipelined stages and one or more loop operations. The method comprises evaluating...
6934938 Method of programming linear graphs for streaming vector computation  
A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each...
6721813 Computer system implementing a system and method for tracking the progress of posted write transactions  
A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem...
6557048 Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof  
A computer system is presented which implements a system and method for ordering input/output (I/O) memory operations. In one embodiment, the computer system includes a processing subsystem and an...
6446193 Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture  
A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second...
6401194 Execution unit for processing a data stream independently and in parallel  
A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic...
6324600 System for controlling movement of data in virtual environment using queued direct input/output device and utilizing finite state machine in main memory with two disjoint sets of states representing host and adapter states  
A method and an apparatus for controlling movement of data between any host and any network including a set of devices in a computing system environment having a main memory with a queuing...
6295597 Apparatus and method for improved vector processing to support extended-length integer arithmetic  
An apparatus and a method for extended-precision vector arithmetic capable of extremely long precision (i.e., precision to as many bits as a user desires or is limited to due to memory,...
6269435 System and method for implementing conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector  
A processor implements conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a...
6202141 Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectors  
A vector multiplication mechanism is provided that partitions vector multiplication operation into even and odd paths. In an odd path, odd data elements of first and second source vectors are...
6073158 System and method for processing multiple received signal sources  
A system and method for time slicing multiple received data streams utilizing multiple processors in such a manner as to ensure that all processors are running at full capability and are...
6061777 Apparatus and method for reducing the number of rename registers required in the operation of a processor  
One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently...
6023752 Digital data apparatus for transferring data between NTDS and bus topology data buses  
A program driver means is disclosed that allows for the exchange of inforion between a NTDS device and a device having a bus topology, especially a VMEbus. The program driver utilizes chain...
RE36183 System for rearranging sequential data words from an initial order to an arrival order in a predetermined order  
A data shuffler of the pipeline type receives successive trains of n sequential data words and rearranges data words in each train according to a predetermined order. It comprises p (p≤n)...
5261113 Apparatus and method for single operand register array for vector and scalar data processing operations  
In a data processing system in which a processing unit can execute both scalar and vector instructions, the use of a single operand register file to store both the scalar operation operands and the...
5091848 Vector processor for merging vector elements in ascending order merging operation or descending order merging operation  
Vector elements are compared in synchronism with the supplying of vector elements to the an operation unit for merging, and the operation to be effected on the individual vector elements is...
5060148 Control system for vector processor with serialization instruction for memory accesses for pipeline operation  
An access instruction pipeline for receiving an access instruction for accessing data to be inputted to the pipeline of a vector processor includes a plurality of buffers for buffering a memory...
5010483 Vector processor capable of indirect addressing  
A vector processor includes a first read circuit for reading a first vector including a plurality of vectors such as a vector having elements denoting a compare key as a search request and a vector...
4974198 Vector processing system utilizing firm ware control to prevent delays during processing operations  
A vector processing system prevents delays in reading microinstructions from a control memory during processing operations. The vector processing system permits a second microinstruction to be read...
4967350 Pipelined vector processor for executing recursive instructions  
A vector computer includes memory 11 for storing vector data, and arithmetic unit 12 for sequentially reading out the vector data from memory 11, performing vector processing based on a pipeline...
4933839 Vector processor  
A vector processor has a discriminator for determining in one machine cycle of an operation unit whether a bit pattern of elements of vector data meets a predetermined condition or not. An output...
4890220 Vector processing apparatus for incrementing indices of vector operands of different length according to arithmetic operation results  
The vector processing apparatus fetches vector operands designated by an instruction from a storage to an operand buffer in a vector processor. The vector processor reads out and processes the...
4853890 Vector processor  
In a vector processor including pipeline processors and means for synchronously controlling each component, there is provided an FIFO memory for temporarily storing the output of each pipeline...
4792893 Selectively recursive pipelined parallel vector logical operation system  
A vector logical operation apparatus includes first and second registers respectively for sequentially receiving first and second sets of vector elements which first and second sets of vector...
4779192 Vector processor with a synchronously controlled operand fetch circuits  
A vector processor for sequentially reading out elements of a plurality of vector operands and sequentially storing the results of operations to the vector operands, comprising: operand counters...
4760545 Vector processing apparatus including vector registers having selectively accessible storage locations  
A vector instruction which designates calculation of vector data or vector data transfer between vector registers and the main memory, is arranged in such a way as to specify an element in the...
4723206 Vector processor  
A vector to be processed consisting of a plurality of partial vectors each having a variable number of vector elements and a key vector consisting of a fixed number of vector elements are...
4710867 Vector processing system  
A vector processing system having a main memory, at least one scalar register, a plurality of vector registers, a functional section for performing predetermined operations for at least a group of...
4677547 Vector processor  
At the point of time at which a segment base address is generated in current loop processing, a segment address displacement for use in the next loop processing is calculated in advance and held in...
4658355 Pipeline arithmetic apparatus  
In a pipeline arithmetic apparatus, an arithmetic operation is divided into a plurality of stages and processed in an overlapping manner in each of the stages. Arithmetic circuits are provided each...
4656581 Vector mask control system  
A vector mask control system capable of processing both operand information and vector mask information associated with the operand information is provided. A vector data operating section and a...
4651274 Vector data processor  
A vector data processor includes a vector index register for consecutively and sequentially storing indirect address vectors, which may then be consecutively and sequentially read out from the...
4128880 Computer vector register processing  
Vector processing in a computer is achieved by means of a plurality of vector registers, a plurality of independent fully segmented functional units, and means for controlling the operation of the...
Matches 1 - 42 out of 42