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7603492 |
Automatic generation of streaming data interface circuit
A streaming data interface device ( 700 ) of a streaming processing system ( 200 ) is automatically generated by selecting a set of circuit parameters ( 610 ) consistent with a set of circuit...
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7526456 |
Method of operation for parallel LCP solver
A method of operating a Linear Complementarity Problem (LCP) solver is disclosed, where the LCP solver is characterized by multiple execution units operating in parallel to implement a competent...
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7506135 |
Histogram generation with vector operations in SIMD and VLIW processor by consolidating LUTs storing parallel update incremented count values for vector data elements
The present invention provides histogram calculation for images and video applications using a SIMD and VLIW processor with vector Look-Up Table (LUT) operations. This provides a speed up of...
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7475222 |
Multi-threaded processor having compound instruction and operation formats
A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded...
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7467288 |
Vector register file with arbitrary vector addressing
A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includes a vector data file comprising a...
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7457938 |
Staggered execution stack for vector processing
In one embodiment, the present invention includes a method for executing an operation on low order portions of first and second source operands using a first execution stack of a processor and...
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7447873 |
Multithreaded SIMD parallel processor with loading of groups of threads
In a multithreaded processing core, groups of threads are executed using single instruction, multiple data (SIMD) parallelism by a set of parallel processing engines. Input data defining objects to...
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7437544 |
Data processing apparatus and method for executing a sequence of instructions including a multiple iteration instruction
A data processing apparatus and method are provided for executing a sequence of instructions including at least one multiple iteration instruction. The data processing apparatus comprises an...
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7434040 |
Copying of unaligned data in a pipelined operation
Methods, computer readable media and computing devices including program instructions are provided for copying unaligned data. One method embodiment includes using 12 execution units to move 16...
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7404065 |
Flow optimization and prediction for VSSE memory operations
In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises...
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7305649 |
Automatic generation of a streaming processor circuit
A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation...
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7293258 |
Data processor and method for using a data processor with debug circuit
A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of...
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7290122 |
Dataflow graph compression for power reduction in a vector processor
A method and apparatus for power reduction in a processor controlled by multiple-instruction control words. A multiple-instruction control word comprises a number of ordered fields, with each...
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7284113 |
Synchronous periodical orthogonal data converter
An orthogonal data converter for converting the components of a sequential vector component flow to a parallel vector component flow. The data converter has an input rotator configured to rotate...
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7257695 |
Register file regions for a processing system
According to some embodiments, a dynamic region in a register file may be described for an operand. The described region may, for example, store multiple data elements, each data element being...
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7206857 |
Method and apparatus for a network processor having an architecture that supports burst writes and/or reads
A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth...
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7200724 |
Two dimensional data access in a processor
A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second...
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7100019 |
Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values
A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface....
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7093103 |
Method for referring to address of vector data and vector processor
The object of the invention is to efficiently perform indirect index vector reference. An element register of a vector register or a scalar register specified in the “index” is divided into...
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7080216 |
Data access in a processor
A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second...
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7000099 |
Large table vectorized lookup by selecting entries of vectors resulting from permute operations on sub-tables
A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data...
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6968445 |
Multithreaded processor with efficient processing for convergence device applications
A multithreaded processor includes an instruction decoder for decoding retrieved instructions to determine an instruction type for each of the retrieved instructions, an integer unit coupled to the...
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6963341 |
Fast and flexible scan conversion and matrix transpose in a SIMD processor
The present invention provides efficient ways to implement scan conversion and matrix transpose operations using vector multiplex operations in a SIMD processor. The present method provides a very...
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6934938 |
Method of programming linear graphs for streaming vector computation
A method for producing a formatted description of a computation representable by a data-flow graph and computer for performing a computation so described. A source instruction is generated for each...
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6924802 |
Efficient function interpolation using SIMD vector permute functionality
A system, method, and computer program product are provided for generating display data. The data processing system loads coefficient values corresponding to a behavior of a selected function in...
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6915411 |
SIMD processor with concurrent operation of vector pointer datapath and vector computation datapath
A digital signal processor (DSP) includes a SIMD-based organization wherein operations are executed on a plurality of single-instruction multiple data (SIMD) datapaths or stages connected in...
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6782470 |
Operand queues for streaming data: A processor register file extension
The register file of a processor includes embedded operand queues. The configuration of the register file into registers and operand queues is defined dynamically by a computer program. The...
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6636828 |
Symbolic calculation system, symbolic calculation method and parallel circuit simulation system
The coefficient matrix, corresponding to the simultaneous linear equations to be solved, is divided into a plurality of row sets. The row sets as divided are processed in a parallel fashion, and...
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6571386 |
Apparatus and method for program optimizing
An optimizer ( 100 ) comprises a memory ( 110 ) and a processor ( 130 ). The memory stores a program ( 200 ) to be optimized and optimization software ( 301 ). Controlled by the optimization...
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6557097 |
Linear vector computation
A processing engine 10 provides computation of an output vector as a linear combination of N input vectors with N coefficients in an efficient manner. The processing engine includes a coefficient...
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6553486 |
Context switching for vector transfer unit
A vector transfer unit for handling transfers of vector data between a memory and a data processor by one or more application programs in a computer system. A compiler identifies the use of vector...
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6470440 |
Vector compare and maximum/minimum generation apparatus and method therefor
An apparatus for compare and maximum/minimum and a method therefor are implemented. Selection circuitry selects a data value signal for outputting between an a pair of vector operands and...
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6446193 |
Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture
A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second...
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6401194 |
Execution unit for processing a data stream independently and in parallel
A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic...
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6385633 |
Method and apparatus for computing complex phase
The phase of a complex number I+jQ is computed using a hybrid lookup table and computation approach suitable for DSP implementation and useful in remote access/networking and wireless applications....
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6385632 |
Fast CORDIC algorithm with sine governed termination
A system and method for evaluating one or more functions using a succession of CORDIC stages/iterations followed by a residual rotation. The succession of CORDIC stages are preferably partitioned...
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6336179 |
Dynamic scheduling mechanism for an asynchronous/isochronous integrated circuit interconnect bus
A first counter sequentially counts a plurality of numbers from respective sources requesting transfer of data. Each of the numbers represents an amount of isochronous data to transfer over the bus...
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6324638 |
Processor having vector processing capability and method for executing a vector instruction in a processor
A processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the...
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6324600 |
System for controlling movement of data in virtual environment using queued direct input/output device and utilizing finite state machine in main memory with two disjoint sets of states representing host and adapter states
A method and an apparatus for controlling movement of data between any host and any network including a set of devices in a computing system environment having a main memory with a queuing...
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6219073 |
Apparatus and method for information processing using list with embedded instructions for controlling data transfers between parallel processing units
In a data processing apparatus, data is transferred in accordance with a meta-instruction embedded in the data. To put it in detail, first of all, a first meta-instruction is read out from an...
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6212622 |
Mechanism for load block on store address generation
A processor employs ordering dependencies for load instruction operations upon store address instruction operations. The processor divides store operations into store address instruction operations...
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6212618 |
Apparatus and method for performing multi-dimensional computations based on intra-add operation
A method and apparatus for including in a processor, instructions for performing multiply-intra-add operations on packed data is described. In one embodiment, a processor is coupled to a memory....
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6195747 |
System and method for reducing data traffic between a processor and a system controller in a data processing system
A system and method for reducing data traffic between the processor and the system controller in a data processing system during the execution of a vector or matrix instruction. When the processor...
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6175907 |
Apparatus and method for fast square root calculation within a microprocessor
An apparatus and method for calculating a square root of an operand in a microprocessor are provided. The microprocessor has a plurality of square root instructions, each of which specifies a...
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6061777 |
Apparatus and method for reducing the number of rename registers required in the operation of a processor
One aspect of the invention relates to a method for operating a processor. In one version of the invention, the method includes the steps of dispatching an instruction; determining a presently...
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6058465 |
Single-instruction-multiple-data processing in a multimedia signal processor
A vector processor architecture provides vector registers of fixed size having data elements of programmable size and type. The type and size for data elements are defined by instructions which...
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6047372 |
Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional...
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6006315 |
Computer methods for writing a scalar value to a vector
A method is provided for writing a scalar value to a vector V1 without reading the vector from a storage device. A scalar value to be written into the vector at a specified position and a scalar...
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5996057 |
Data processing system and method of permutation with replication within a vector register file
The data processing system of the present invention loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input...
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5991865 |
MPEG motion compensation using operand routing and performing add and divide in a single instruction
A routable operand and selectable operation processor multimedia extension unit is employed to motion compensate MPEG video using improved vector processing. A vector processing unit executes an...
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