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7519800 Apparatus and method for enforcing homogeneity within partitions of heterogeneous computer systems  
A heterogeneous computer system has multiple interconnected cells, each cell has multiple primary processors of the same Instruction Set Architecture (ISA) type, but different cells may have...
7480797 Method and system for preventing current-privilege-level-information leaks to non-privileged code  
Various embodiments of the present invention introduce privilege-level mapping into a computer architecture not initially designed for supporting virtualization. Privilege-level mapping can, with...
7404065 Flow optimization and prediction for VSSE memory operations  
In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises...
7219212 Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion  
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one...
7100019 Method and apparatus for addressing a vector of elements in a partitioned memory using stride, skip and span values  
A system and method for calculating memory addresses in a partitioned memory in a processing system having a processing unit, input and output units, a program sequencer and an external interface....
7069557 Network processor which defines virtual paths without using logical path descriptors  
A virtual path feature in which several virtual channels share an assigned amount of bandwidth is implemented in a network processor. The network processor maintains a schedule indicative of...
7043607 Information processing system and cache flash control method used for the same  
The vector unit 21 outputs a first flash address to the flash address array 24 . The vector unit 31 outputs a second flash address to the flash address array 34 . In the master unit 2 , the...
6963341 Fast and flexible scan conversion and matrix transpose in a SIMD processor  
The present invention provides efficient ways to implement scan conversion and matrix transpose operations using vector multiplex operations in a SIMD processor. The present method provides a very...
6957324 Computer system and method of controlling computation  
A vector computer system includes a plurality of memory banks 40 , a vector processor 11 , and a plurality of additional processing units 30 each of which is connected to one of the memory...
6865517 Aggregation of sensory data for distributed decision-making  
A method, apparatus and computer product that enables a processor associated with a node in a computer system having various nodes, the nodes having sensors which provide data, and the nodes being...
6816960 Cache consistent control of subsequent overlapping memory access during specified vector scatter instruction execution  
A vector artchitecture processing unit according to the present invention comprises a vector scatter (VSC) address coincidence detection unit 3 that comprises registers in which an area start...
6813701 Method and apparatus for transferring vector data between memory and a register file  
A compiler and vector data transfer instructions for use in a vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. The compiler...
6742106 Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page  
A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the...
6665749 Bus protocol for efficiently transferring vector data  
The present invention provides a bus architecture for a data processing system that improves transfers of vector data using a vector transfer unit (VTU). An external bus is coupled between the...
6625720 System for posting vector synchronization instructions to vector instruction queue to separate vector instructions from different application programs  
A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector instructions are used for transferring the vector data between memory...
6571386 Apparatus and method for program optimizing  
An optimizer ( 100 ) comprises a memory ( 110 ) and a processor ( 130 ). The memory stores a program ( 200 ) to be optimized and optimization software ( 301 ). Controlled by the optimization...
6484220 Transfer of data between processors in a multi-processor system  
A method for transferring data between devices in a computer system. In a preferred embodiment, a requesting device broadcasts a request for data. Each of a plurality of devices within the computer...
6336179 Dynamic scheduling mechanism for an asynchronous/isochronous integrated circuit interconnect bus  
A first counter sequentially counts a plurality of numbers from respective sources requesting transfer of data. Each of the numbers represents an amount of isochronous data to transfer over the bus...
6324611 Physical layer interface and method for arbitration over serial bus using digital line state signals  
A physical layer interface for a serial bus includes a controller for producing parallel data representing a near-end line state of the serial bus. A line transmitter is connected to the controller...
6308250 Method and apparatus for processing a set of data values with plural processing units mask bits generated by other processing units  
A method and system for operating a computing system having multiple processing units. According to a new machine instruction, called the iota instruction, the computing system operates on a vector...
6253304 Collation of interrupt control devices  
A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one...
6202130 Data processing system for processing vector data and method therefor  
A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a...
6141673 Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions  
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus...
6009505 System and method for routing one operand to arithmetic logic units from fixed register slots and another operand from any register slot  
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional...
5991865 MPEG motion compensation using operand routing and performing add and divide in a single instruction  
A routable operand and selectable operation processor multimedia extension unit is employed to motion compensate MPEG video using improved vector processing. A vector processing unit executes an...
5961628 Load and store unit for a vector processor  
An apparatus coupled to a requesting unit and a memory. The apparatus includes a data path and a request control circuit. The data path is coupled to the requesting unit and the memory. The data...
5918062 Microprocessor including an efficient implemention of an accumulate instruction  
An execution unit configured to perform a plurality of arithmetic operations using the same set of operands. These operands include corresponding input vector values in each of a plurality of input...
5918027 Data processor having bus controller  
A bus controller connects to external devices having both a separate-type bus interface and a multiplexed-type bus interface simultaneously by providing a dedicated address terminal and a...
5890007 Multi-cluster parallel processing computer system  
A multi-cluster computer system includes a plurality of clusters and a crossbar network for connecting the clusters. Each cluster includes processors, a shared memory, local network, data holding...
5881302 Vector processing unit with reconfigurable data buffer  
A vector processing unit includes data buffers between a storage and a vector processor. Each of the data buffers is divided into four virtual buffers. Each virtual buffer can store 16 words of...
5802384 Vector data bypass mechanism for vector computer  
A bypass mechanism in a vector computer is disclosed. The vector register bypasses data to be written in the inner registers from input or output of the write data register. The bypass mechanism is...
5771392 Encoding method to enable vectors and matrices to be elements of vectors and matrices  
A method and system for encoding nested matrices and vectors. The system can be used in a live mathematical document program executed on a computer processor. The mathematical document program...
5669013 System for transferring M elements X times and transferring N elements one time for an array that is X*M+N long responsive to vector type instructions  
A plurality of special multi-element registers, called "vector registers" herein, are incorporated into a scalar computer. The vector registers are controlled to sequence the transfer of vector...
5649144 Apparatus, systems and methods for improving data cache hit rates  
A processing system is provided which generates a memory address and presents the memory address to a cache to retrieve corresponding data when such corresponding data is encached therein. The...
5603046 Method for complex data movement in a multi-processor data processing system  
A method for complex data movement in a multi-processor data processing system. In one embodiment, the multi-processor data processing system (10) includes an array (12) of data processors (50-65),...
5475849 Memory control device with vector processors and a scalar processor  
A memory control unit connected to a scalar processor having a buffer for storing a copy of block data of a main storage and a vector processor having a store requester for writing data into the...
5428803 Method and apparatus for a unified parallel processing architecture  
A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system....
5418973 Digital computer system with cache controller coordinating both vector and scalar operations  
A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit, and a cache controller unit. The...
5408677 Vector parallel computer  
A back-end vector parallel computer system suitable for supercomputing in engineering and science, comprising N vector processor units and a cubic array of N 3 memory banks which are shared by N...
5319791 System for predicting memory fault in vector processor by sensing indication signal to scalar processor to continue a next vector instruction issuance  
A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the...
5276902 Memory access system for vector data processed or to be processed by a vector processor  
A memory accessing system for vector data processed, or to be processed, by a vector processing apparatus comprising plural vector processing units, each unit performing vector data processing for...
5247695 Vector processor with byte access of memory  
A vector processor in which input/output of vector data to and from a vector register is effected by a load/store pipeline from a main memory, includes a load pipe for reading data of a plural-byte...
5201058 Control system for transferring vector data without waiting for transfer end of the previous vector data  
A data transfer controller controls transfer of vector data from a first device to a second device, and the vector data consists of a plurality of elements. The data transfer controller includes a...
5081573 Parallel processing system  
A parallel processing system utilizes a plurality of simultaneously operable arithmetic units to provide matrix-vector products, with each of the arithmetic units implementing the matrix-vector...
5063497 Apparatus and method for recovering from missing page faults in vector data processing operations  
In a data processing system employing virtual memory techniques and capable of performing a plurality of overlapping scalar and vector data processing operations, apparatus and method are provided...
5060148 Control system for vector processor with serialization instruction for memory accesses for pipeline operation  
An access instruction pipeline for receiving an access instruction for accessing data to be inputted to the pipeline of a vector processor includes a plurality of buffers for buffering a memory...
5010483 Vector processor capable of indirect addressing  
A vector processor includes a first read circuit for reading a first vector including a plurality of vectors such as a vector having elements denoting a compare key as a search request and a vector...
4985827 Computer for synchronized read and write of vector data  
A computer comprising a circuit for writing a group of ordered data elements onto the main storage; a circuit for reading said group of data from the main storage; and a circuit which is connected...
4974145 Processor system including a paging processor for controlling paging between a main storage and an extended storage  
A vector processor having a scalar procesing unit, a vector processing unit, a main storage unit, an extended storage unit, a storage control unit, and a paging processor unit, in which the storage...
4949247 System for transferring multiple vector data elements to and from vector memory in a single operation  
Apparatus for performing vector operations on the data elements of vectors includes a vector processor for performing arithmetic operations on the elements, a vector memory for storing the data...
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