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7624251 Instructions for efficiently accessing unaligned partial vectors  
One embodiment of the present invention provides a processor that is configured to execute load-swapped-partial instructions. An instruction fetch unit within the processor is configured to fetch...
7620797 Instructions for efficiently accessing unaligned vectors  
One embodiment of the present invention provides a processor which is configured to execute load-swapped instructions, which are possibly directed to unaligned source address. The processor is...
7529907 Method and apparatus for improved computer load and store operations  
Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by...
7505460 Address validating data structure used for validating addresses  
Provided is an address validating data structure used for validating addresses. A data structure comprising a plurality of arrays is buffered. Each array includes a plurality of words, wherein one...
7480787 Method and structure for pipelining of SIMD conditional moves  
A mask is first generated in a general-purpose integer register. The mask is generated by executing a single instruction multiple data (SIMD) instruction on a plurality of operands stored in a...
7467286 Executing partial-width packed data instructions  
A method and apparatus are provided for executing packed data instructions. According to one aspect of the invention, a processor includes registers, a register renaming unit coupled to the...
7467288 Vector register file with arbitrary vector addressing  
A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includes a vector data file comprising a...
7428628 Method and apparatus for management of control flow in a SIMD device  
A single instruction multiple data processing device includes a plurality of processing elements. Each processing element includes an execute mask count register storing a plurality of bits. The...
7404065 Flow optimization and prediction for VSSE memory operations  
In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises...
7293258 Data processor and method for using a data processor with debug circuit  
A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of...
7219213 Flag bits evaluation for multiple vector SIMD channels execution  
According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might...
7197625 Alignment and ordering of vector elements for single instruction multiple data processing  
The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a...
7093102 Code sequence for vector gather and scatter  
Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required...
7058794 Apparatus and method for masked move to and from flags register in a processor  
A method and apparatus are provided for storing a flags register in a processor. In response to a macro instruction directing the store operation, such as a push flags macro instruction, a mask is...
7028171 Multi-way select instructions using accumulated condition codes  
The present invention relates to a method and system for providing an N-way select instruction in a processor. Specifically, a method for providing an N-way select instruction includes decoding an...
7003653 Method for rapid interpretation of results returned by a parallel compare instruction  
A method for rapidly mapping a bitmask returned by a Single Instruction Multiple Data (SIMD) computer compare instruction is provided. A user supplied partitioned mapping variable includes multiple...
7000099 Large table vectorized lookup by selecting entries of vectors resulting from permute operations on sub-tables  
A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data...
6963341 Fast and flexible scan conversion and matrix transpose in a SIMD processor  
The present invention provides efficient ways to implement scan conversion and matrix transpose operations using vector multiplex operations in a SIMD processor. The present method provides a very...
6931511 Parallel vector table look-up with replicated index element vector  
Methods and apparatuses for looking up vectors in parallel using vector table look up operations. In one aspect of the invention, a method to look up a plurality of data items indexed by a vector...
6922771 Vector floating point unit  
The present invention provides a vector floating point unit (FPU) comprising a product-terms bus, a summation bus, a plurality of FIFO (first in first out) registers, a crossbar operand multiplexor...
6922764 Memory, processor system and method for performing write operations on a memory region  
A memory is provided which has a memory region for storing data, an input for receiving a data bundle with a plurality of temporally sequential data blocks and an input for receiving a data mask...
6918029 Method and system for executing conditional instructions using a test register address that points to a test register from which a test code is selected  
A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on said operands. Each instruction also...
6904510 Data processor having a respective multiplexer for each particular field  
A data processor that can perform instructions in parallel on respective fields in an operand includes a respective multiplexer for each of the respective fields. Each respective multiplexer is...
6865517 Aggregation of sensory data for distributed decision-making  
A method, apparatus and computer product that enables a processor associated with a node in a computer system having various nodes, the nodes having sensors which provide data, and the nodes being...
6789180 Method and apparatus for mask and/or counter address registers readback on the address bus in synchronous single and multi-port memories  
An apparatus comprising a memory device and one or more control circuits. The memory device may be configured to store and retrieve data. The one or more control circuits may be configured to...
6560698 Register change summary resource  
A microcontroller provides a register change summary resource for summarizing register changes. Selected system registers within each resource are coupled to bits in resource change registers of...
6530011 Method and apparatus for vector register with scalar values  
A method and an apparatus for implementing mixed scalar and vector values in a digital processing system. In one embodiment, a digital processing system, which contains processing unit and...
6530015 Accessing a test condition for multiple sub-operations using a test register  
A method and system of executing computer instructions is described. Each instruction defines first and second operands and an operation to be carried out on said operands. Each instruction also...
6496916 System for flexible memory paging in partitioning memory  
A memory paging method and apparatus using a memory paging register and a memory paging mask register. The invention has particular application in the partition of memory used by more than one...
6324638 Processor having vector processing capability and method for executing a vector instruction in a processor  
A processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the...
6308250 Method and apparatus for processing a set of data values with plural processing units mask bits generated by other processing units  
A method and system for operating a computing system having multiple processing units. According to a new machine instruction, called the iota instruction, the computing system operates on a vector...
6298431 Banked shadowed register file  
An apparatus and method for improving processor performance during multithreaded processing based on the use of a banked shadowed register file for minimizing thread switch overhead.
6269435 System and method for implementing conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector  
A processor implements conditional vector operations in which an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a...
6266759 Register scoreboarding to support overlapped execution of vector memory reference instructions in a vector processor  
A vector-processor SIMD RISC computer system uses virtual addressing and overlapped instruction execution. Indicators for each of the architected registers assume different states when an...
6223277 Data processing circuit with packed data structure capability  
A packed data structure processor (25) is disclosed. The packed data structure processor (25) includes a register file (24) of multiple registers (REG0 through REG31), each of which is connected to...
6212622 Mechanism for load block on store address generation  
A processor employs ordering dependencies for load instruction operations upon store address instruction operations. The processor divides store operations into store address instruction operations...
6202141 Method and apparatus for performing vector operation using separate multiplication on odd and even data elements of source vectors  
A vector multiplication mechanism is provided that partitions vector multiplication operation into even and odd paths. In an odd path, odd data elements of first and second source vectors are...
6141673 Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions  
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus...
6115805 Non-aligned double word fetch buffer  
A non-aligned double word fetch buffer is integrated into a digital signal processor to handle non-aligned double word (32 bit) fetches. When a misaligned double word fetch is detected, the buffer...
6098162 Vector shift functional unit for successively shifting operands stored in a vector register by corresponding shift counts stored in another vector register  
Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a...
6061521 Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle  
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional...
6058465 Single-instruction-multiple-data processing in a multimedia signal processor  
A vector processor architecture provides vector registers of fixed size having data elements of programmable size and type. The type and size for data elements are defined by instructions which...
6047372 Apparatus for routing one operand to an arithmetic logic unit from a fixed register slot and another operand from any register slot  
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional...
5996066 Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions  
An optimized, superscalar microprocessor architecture for supporting graphics operations in addition to the standard microprocessor integer and floating point operations. A number of specialized...
5996057 Data processing system and method of permutation with replication within a vector register file  
The data processing system of the present invention loads three input operands, including two input vectors and a control vector, into vector registers and performs a permutation of the two input...
5944811 Superscalar processor with parallel issue and execution device having forward map of operand and instruction dependencies  
In a superscalar processor for fetching a prescribed peak number of instructions in parallel in each period until such instructions are fetched to a predetermined peak number, such as ten, an...
5940625 Density dependent vector mask operation control apparatus and method  
A vector processing system which uses vector masks to determine whether or not to perform operations on operands corresponding to bit positions within the mask is disclosed. An approximation of the...
5903769 Conditional vector processing  
A vector processor with a vector mask control unit provides an efficient approach for execution of conditional loops by a vector processor. The vector mask control unit includes respective vector...
5890006 Apparatus for extracting instruction specific bytes from an instruction  
A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. In one embodiment, to expedite the dispatch of instructions, the...
5832290 Apparatus, systems and method for improving memory bandwidth utilization in vector processing systems  
Vector register circuitry is provided which includes a vector register file comprising at least one vector register having a plurality of elements, the vector register file further having at least...
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