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7627770 Apparatus and method for automatic low power mode invocation in a multi-threaded processor  
A processor comprises a processor core executing multiple threads. A bifurcated thread scheduler includes an internal processor core component and an external processor core component. The...
7627739 Optimization of a hardware resource shared by a multiprocessor  
Embodiments include a device and a method. In an embodiment, a method applies a first resource management strategy to a first resource associated with a first processor and executes an instruction...
7610466 Data processing system using independent memory and register operand size specifiers and method thereof  
Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of...
7603566 Authenticated process switching on a microprocessor  
A microprocessor includes a first information holding unit, a second information holding unit, and a switching authorization unit. The first information holding unit holds process identification...
7596683 Switching processor threads during long latencies  
In one embodiment, the present invention includes an apparatus to determine whether execution of an instruction of a first thread may require a long latency and switch to a second thread if the...
7577823 Wake-up and sleep conditions of processors in a multi-processor system  
The present invention relates to a multi-processor computer system comprising at least two processors for parallel execution of processes, at least two cache memory units, each being...
7568083 Memory mapped register file and method for accessing the same  
A register file for a data processing system comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of memory locations. Each memory location is addressable by...
7529916 Data processing apparatus and method for controlling access to registers  
A data processing apparatus and method are provided for controlling access to registers. The data processing apparatus comprises a processing unit for performing data processing operations on data...
7526693 Initial decision-point circuit operation mode  
A circuit that includes a controller and at least one control I/O pin. When the controller is placed into an initial state, the controller initializes the circuit into an initial operation mode....
7526632 System, apparatus and method for implementing multifunctional memory in reconfigurable data path processing  
A system, apparatus and a method for implementing multifunctional memories is disclosed. The multifunctional memories perform a variety of functions during execution of extended instructions in a...
7509480 Selection of ISA decoding mode for plural instruction sets based upon instruction address  
An apparatus and method are provided that enable a multiple instruction set architecture (ISA) central processing unit (CPU) to distinguish between different program instructions corresponding to...
7503048 Scheduling synchronization of programs running as streams on multiple processors  
Systems and methods for scheduling program units that are part of a process executed within an operating system are disclosed. Additionally, at least one thread is started within the operating...
7493472 Meta-address architecture for parallel, dynamically reconfigurable computing  
A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a...
7487330 Method and apparatus for transferring control in a computer system with dynamic compilation capability  
In a dynamically compiling computer system, a system and method for efficiently transferring control from execution of an instruction in a first representation to a second representation of the...
7478184 Integrated circuit device including processor selection in a multiprocessor system  
An integrated circuit device in which a CPU not to be used of a plurality of CPUs formed on one chip can easily be disconnected by an external signal in order to reduce the costs of developing an...
7457886 System and method for input/output scheduling  
A system and method for Input/Output scheduling are described herein. In one embodiment, the method includes installing a plurality of Input/Output (I/O) schedulers to schedule I/O requests for a...
7437532 Memory mapped register file  
A memory mapped register file is disclosed for a data processing system that comprises a memory unit, input ports, and output ports. The memory unit includes a plurality of registers addressable by...
7430678 Low power operation control unit and program optimizing method  
An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit...
7424595 System for managing circuitry of variable function information processing circuit and method for managing circuitry of variable function information processing circuit  
Configuration management information having circuit configuration information for altering a circuit configuration of an FPGA ( 12 ) is stored in a memory ( 13 ), the configuration management...
7421571 Apparatus and method for switching threads in multi-threading processors  
A multi-threaded processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the...
7398410 Processor employing a power managing mechanism and method of saving power for the same  
A processor includes a plurality of execution units configured to execute instructions, a pre-decoder configured to sieve out a power-switching instruction from the instructions, and a power...
7395416 Computer processing system employing an instruction reorder buffer  
A method and a system for operating a plurality of processors that each includes an execution pipeline for processing dependence chains, the method comprising: configuring the plurality of...
7389405 Digital signal processor architecture with optimized memory access for code discontinuity  
A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code...
7366891 Methods and apparatus to provide dual-mode drivers in processor systems  
Methods and apparatus to provide dual-mode drivers in a processor system are disclosed. An example method disclosed herein comprises including operating system (OS) agnostic mode services that are...
7363625 Method for changing a thread priority in a simultaneous multithread processor  
An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in...
7356673 System and method including distributed instruction buffers for storing frequently executed instructions in predecoded form  
A system and method is provided for processing a first instruction set and a second instruction set in a single processor. The method includes storing a plurality of instructions of the second...
7356670 Data processing system  
A multiprocessor data processing system is described wherein the processors communicate to each other via a shared memory. Each of the processors comprises an administration unit ( 18 a ) and a...
7218562 Recovering bit lines in a memory array after stopped clock operation  
In one embodiment, an apparatus comprises a plurality of memory cells; first and second bit lines coupled to the plurality of memory cells; a first and second bit line precharge circuits coupled to...
7203823 Partial and start-over threads in embedded real-time kernel  
Methods and apparatus for implementing partial and start-over threads in a kernel of an operating system are disclosed. In a computing system having at least one CPU, registers for executing...
7197627 Multiple processor arrangement for conserving power  
A processing arrangement for a computer comprising: first processor means (1) for processing a first set of instructions; and second processor means (2) for processing a second set of instructions,...
7197577 Autonomic input/output scheduler selector  
The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped...
7194601 Low-power decode circuitry and method for a processor having multiple decoders  
A processor includes first decoder logic capable of decoding a plurality of encoded instructions comprising a first instruction set, the first decoder logic having an input to receive an encoded...
7174443 Run-time reconfiguration method for programmable units  
A method of run-time reconfiguration of a programmable unit is provided, the programmable unit including a plurality of reconfigurable function cells in a multidimensional arrangement. An event is...
7159099 Streaming vector processor with reconfigurable interconnection switch  
A re-configurable, streaming vector processor ( 100 ) is provided which includes a number of function units ( 102 ), each having one or more inputs for receiving data values and an output for...
7155726 System for dynamic registration of privileged mode hooks in a device  
Methods and apparatuses are provided for dynamic registration of privileged mode hooks in a device that can operate in a privileged mode and a non-privileged mode. A data structure is provided...
7155600 Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor  
A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching...
7139905 Dynamic endian switching  
The dynamic switching of a bi-endian processor between endian modes is described. A device having the bi-endian processor may also have an endian select circuit. The endian select circuit may...
7134047 Firmwave mechanism for correcting soft errors  
A computer system includes processor having dual execution cores and a non-volatile memory that stores an error recovery routine. The processor's execution cores operate in lock step when the...
7134002 Apparatus and method for switching threads in multi-threading processors  
An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit and a second instruction fetch unit. A multi-thread scheduler unit is coupled to the...
7127594 Multiprocessor system and program optimizing method  
A multiprocessor system capable of responding to various types of processing to improve the processing efficiency of the entire system. Each of a plurality of processors holds information...
7124286 Establishing an operating mode in a processor  
A processor supports a processing mode in which the address size is greater than 32 bits and the operand size may be 32 or 64 bits. The address size may be nominally indicated as 64 bits, although...
7114089 System for controlling operation of a processor based on information contained within instruction word  
An instruction word is used to transfer information about whether the instruction word pertains to mode setting of a functional block. Instruction words included in the program code are processed...
7100063 Low power operation control unit and program optimizing apparatus  
An objective is to perform a low power operation of a microprocessor on the pipeline stage of an instruction decode and a preceding pipeline stage without the necessity for increasing a circuit...
7082518 Interruptible digital signal processor having two instruction sets  
The present invention relates to a digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available...
7080362 Java virtual machine hardware for RISC and CISC processors  
A hardware Java™ accelerator is provided to implement portions of the Java™ virtual machine in hardware in order to accelerate the operation of the system on Java™ bytecodes. The Java™...
7076637 System for providing transitions between operating modes of a device  
System for providing transitions between operating modes of a device. The system includes a method for providing transitions between a privileged and a non-privileged operating mode. The method...
7058791 Establishing a mode indication responsive to two or more indications  
A processor generates a mode indication based on two or more other indications. The mode indication is indicative of whether or not a particular mode is active in the processor. Each indication is...
7028197 System and method for electrical power management in a data processing system using registers to reflect current operating conditions  
A processor is disclosed including a register, functional unit(s), and a control unit. The register stores multiple bits, wherein one or more of the bits has a value representing a current...
6993640 Apparatus for supporting a logically partitioned computer system  
A processor supports logical partitioning of hardware resources including real address spaces of a computer system. An ultra-privileged supervisor process, called a hypervisor, regulates the...
6973562 Establishing an operating mode in a processor  
A processor supports a processing mode in which the address size is greater than 32 bits and the operand size may be 32 or 64 bits. The address size may be nominally indicated as 64 bits, although...
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