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7620796 |
System and method for acceleration of streams of dependent instructions within a microprocessor
A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a...
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7478373 |
Kernel emulator for non-native program modules
Described herein is a technology facilitating the operation of non-native program modules within a native computing platform. This invention further generally relates to a technology facilitating...
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7383425 |
Massively reduced instruction set processor
This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to...
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7337443 |
Method and apparatus for processing program threads
A procedure identifies a program image and generates a basic block flow graph associated with the program image. Execution of the program image is benchmarked and the basic block flow graph is...
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7225436 |
Java hardware accelerator using microcode engine
A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level...
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7069423 |
Microcomputer
A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6 , and made accessible in parallel by third buses XAB and XDB and second buses...
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7068394 |
Effects processor for compact printer
An effects processor for an effects module. The effects processor comprises a RISC processor, a DSP for fast integer multiplication and a small memory. The processor uses VARK language and a lookup...
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6978233 |
Method for emulating multi-processor environment
A method of and an apparatus for performing efficient software emulation of a multi-processor target computer by a host computer. The software technique permits multiple processors to be emulated...
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6948050 |
Single integrated circuit embodying a dual heterogenous processors with separate instruction handling hardware
A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit...
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6832306 |
Method and apparatus for a unified RISC/DSP pipeline controller for both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions
Disclosed is a method and apparatus for a unified RISC/DSP pipeline controller to control the execution of both reduced instruction set computer (RISC) control instructions and digital signal...
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6816750 |
System-on-a-chip
A system 100 fabricated on a single integrated circuit chip includes a microprocessor 101 operating from a high speed bus 102 and a peripheral bus 103 operating in conjunction with high...
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6779107 |
Computer execution by opportunistic adaptation
A microprocessor chip and methods for execution by the microprocessor chip. Instruction pipeline circuitry has first and second correct modes for processing at least some instructions. A plurality...
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6766515 |
Distributed scheduling of parallel jobs with no kernel-to-kernel communication
A system and a method of scheduling a plurality of threads from a multi-threaded program. A shared arena is provided in user memory, wherein the shared arena includes a register save area for each...
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6766438 |
RISC processor with a debug interface unit
The present invention provides a RISC processor with a debug interface unit that enables the external replication of the data processing sequence within a RISC processor for debug purposes. The...
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6728866 |
Partitioned issue queue and allocation strategy
A microprocessor and method of processing instructions for addressing timing assymetries are disclosed. A sequence of instructions including a first instruction and a second instruction are...
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6691305 |
Object code compression using different schemes for different instruction types
A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption of a complete system comprising a...
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6654874 |
Microcomputer systems having compressed instruction processing capability and methods of operating same
Microcomputer systems include an instruction processor therein that can process both normal length instructions and compressed instructions. The normal length instructions and the compressed...
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6651159 |
Floating point register stack management for CISC
A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose...
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6615341 |
Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control
A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning...
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6542981 |
Microcode upgrade and special function support by executing RISC instruction to invoke resident microcode
A method and apparatus for invoking microcode instructions resident on a processor by executing a special RISC instruction on the processor such that special functions are provided. In one...
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6499100 |
Enhanced instruction decoding
When decoding instructions of a program to be executed in a central processing unit comprising pipelining facilities for fast instruction decoding, part of the decoding is executed or the decoding...
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6477636 |
Application-specific integrated circuit for processing defined sequences of assembler instructions
The invention relates to an application-specific integrated circuit (ASIC) for processing defined sequences of assembler instructions (TASKs). To improve data throughput in applications with high...
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6425071 |
Subsystem bridge of AMBA's ASB bus to peripheral component interconnect (PCI) bus
A method and apparatus to bridge between the PCI bus and a RISC processor interface bus. In one embodiment, the present invention is a single-ASIC implementation rather than a design using multiple...
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6385714 |
Data processing apparatus
A data processing apparatus uses a stored-program method to execute an operation instructed by an instruction word that includes a register designation code as an operand. A plurality of work...
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6349384 |
System, apparatus and method for processing instructions
A data processing system comprises means for identifying and replacing instructions to jump to functions having known prolog instructions with modified jump instructions, means for storing the...
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6330660 |
Method and apparatus for saturated multiplication and accumulation in an application specific signal processor
An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation...
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6317803 |
High-throughput interconnect having pipelined and non-pipelined bus transaction modes
A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible...
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6314508 |
RISC type microprocessor and information processing apparatus
A general purpose register stores a 16-bit fixed length instruction. A bypass circuit speedily outputs the result of a comparison instruction when the next conditional branch instruction is...
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6308253 |
RISC CPU instructions particularly suited for decoding digital signal processing applications
A reduced programmable controller for an extensible digital signal processing architecture supports particular instructions to facilitate common digital signal processing operations. These...
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6298432 |
One-chip microcomputer including RISC processor and one or more coprocessors having control registers mapped as internal registers for the RISC processor
A one-chip microcomputer including a Reduced Instruction Set Computer (RISC) type processor and one or more coprocessors for performing processes independent from said RISC type processor. The RISC...
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6292881 |
Microprocessor, operation process execution method and recording medium
A microprocessor capable of executing a process instruction having at least one RISC type instruction is constructed to include an instruction decoding section for decoding a microcode including...
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6272620 |
Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation
A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the...
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6260088 |
Single integrated circuit embodying a risc processor and a digital signal processor
A single integrated circuit includes first and second data processors operating on different instruction sets independently operating on disjoint programs and data. The single integrated circuit...
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6237080 |
Executable programs
A computer having a reduced instruction computer (RISC) architecture has a RISC central processing unit (CPU)(1) coupled to a RAM memory (3) and to a flash ROM memory (4). A set of compressed...
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6233492 |
Process control system and method for transferring process data therefor
A process control system includes a plurality of machine controllers for individually controlling a plurality of process chambers and a main controller for controlling the machine controllers. Each...
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6223275 |
Microprocessor with reduced instruction set limiting the address space to upper 2 Mbytes and executing a long type register branch instruction in three intermediate instructions
A 32-bit RISC processor is disclosed. The bit length of the instruction set is fixed to 16 bits. SLIL and SLIH instructions that cause the address space of 4 Gbytes to be limited to upper 2 Mbytes...
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6161171 |
Apparatus for pipelining sequential instructions in synchronism with an operation clock
A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two...
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6134653 |
RISC processor architecture with high performance context switching in which one context can be loaded by a co-processor while another context is being accessed by an arithmetic logic unit
A RISC processor includes a sequencer, a register ALU (RALU), data RAM, and a coprocessor interface. The sequencer includes an N×32 bit instruction RAM which is booted from external memory through...
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6134648 |
Method and apparatus for performing an operation mulitiple times in response to a single instruction
A method for operating a Reduced Instruction Set Computer (RISC) processor that executes normal RISC instructions and special RISC instructions. The method comprises the step of controlling the...
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6134646 |
System and method for executing and completing store instructions
In a processor, store instructions are divided or cracked into store data and store address generation portions for separate and parallel execution within two execution units. The address...
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6119223 |
Map unit having rapid misprediction recovery
A processor employing a map unit including register renaming hardware is shown. The map unit may assign virtual register numbers to source registers by scanning instruction operations to detect...
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6115803 |
Parallel computer which verifies direct data transmission between local memories with a send complete flag
A parallel computer including a plurality of processing elements, each of processing elements comprising a flag address holding unit for temporarily holding an address of a send complete flag of a...
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6101596 |
Information processor for performing processing without register conflicts
An information processor is capable of eliminating register conflict in short and long latency processes and for attaining high-speed pipeline processing through efficient use of registers. The...
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6085310 |
Method and apparatus for performing an operation multiple times in response to a single instruction
A method for operating a Reduced Instruction Set Computer (RISC) processor that executes mormal RISC instructions and special RISC instructions. The method comprises the step of controlling the...
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6079013 |
Multiprocessor serialization with early release of processors
A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode...
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6049864 |
Method for scheduling a flag generating instruction and a subsequent instruction by executing the flag generating instruction in a microprocessor
A method for scheduling a flag generating instruction and a subsequent instruction. The subsequent instruction has a data dependency on the flag generating instruction. The flag generating...
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6021484 |
Dual instruction set architecture
A system and method for executing CISC instructions in a RISC environment are disclosed. A mapper/interface circuit receives CISC instructions which can be from an x86 instruction set, translates...
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6018796 |
Data processing having a variable number of pipeline stages
A data processor comprises a processing unit which processes an instruction in pipeline stages, the number of which is switchable between n and m, m being a larger number than n. The data processor...
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6012137 |
Special purpose processor for digital audio/video decoding
A special purpose reduced instruction set central processing unit (RISC CPU) for controlling digital audio/video decoding. The instruction set includes flow control instructions which incorporate...
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6009508 |
System and method for addressing plurality of data values with a single address in a multi-value store on FIFO basis
A computer system has instructions which have a reduction in the number of address bits relative to the number of data items that may be held during instruction execution. The instruction set...
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