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7612652 Battery activation circuit  
A system and method for selectively activating a device based on an activate command. A circuit, in low power mode, listens for an activate command. The activate command includes a preamplifer...
RE40741 System and method for synchronization of video display outputs from multiple PC graphics subsystems  
A system and method for synchronization of video raster display outputs from multiple PC graphics subsystems to facilitate synchronized output onto multiple displays are disclosed. The system and...
7536533 MCU based motor controller with pre-load register and DMA controller  
A method is disclosed for generating a sequential pattern of motor control instructions under control of a microcontroller for the purpose of controlling a motor. A pattern of motor control...
7526693 Initial decision-point circuit operation mode  
A circuit that includes a controller and at least one control I/O pin. When the controller is placed into an initial state, the controller initializes the circuit into an initial operation mode....
7484069 Watchpointing unaligned data accesses  
A data processing system incorporating watchpoint registers is provided. The memory accesses to be detected may be unaligned memory accesses. The watchpoint may operate in a normal mode and also in...
7441100 Processor synchronization in a multi-processor computer system  
A method for synchronizing a plurality of processors of a multi-processor computer system on a synchronization point is disclosed. The method includes triggering a first set of processors, using a...
7437521 Multistream processing memory-and barrier-synchronization method and apparatus  
A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that...
7421384 Semiconductor integrated circuit device and microcomputer development supporting device  
During software development, a multichip module is used which encloses a target chip and a development chip in one package. A CPU of the development chip fetches instructions from a flash memory in...
7280539 Data driven type information processing apparatus  
In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other...
7243212 Processor-controller interface for non-lock step operation  
Method and apparatus for non-lock-step operation between a processor and a controller is described. An instruction is provided from the processor to the controller. A busy signal is provided from...
7237216 Clock gating approach to accommodate infrequent additional processing latencies  
A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more...
7197627 Multiple processor arrangement for conserving power  
A processing arrangement for a computer comprising: first processor means (1) for processing a first set of instructions; and second processor means (2) for processing a second set of instructions,...
7103701 Memory bus interface  
An interface allows communication between a host device coupled to a host bus and a target device coupled to a target bus. First, the interface receives the address of the target device from the...
7010612 Universal serializer/deserializer  
A universal serializer/deserializer (“ser/des”) is disclosed that provides hardware implemented modules of those functions determined to be most applicable to a communications protocol....
6772326 Interruptible and re-entrant cache clean range instruction  
A digital system and method of operation is provided in which a method is provided for cleaning a range of addresses in a storage region specified by a start parameter and an end parameter. An...
6751788 Method of testing computer software  
A method of testing the ability of software modules, each executing particular functions, in a device to cooperate using machine code sequences contained in executing software modules, checks the...
6748507 Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory  
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
6678766 Synchronous communication bus and process for synchronous communication between circuit modules  
A synchronous communication bus for transferring data between circuit modules ( 2 ), which are connected to the communication bus, having at least one data bus ( 1, 3 ), a control bus ( 4 ) and a...
6578136 Magnetic disc control apparatus with parallel data transfer between disc control unit and encoder circuit  
A disc storage apparatus includes at least one disc having at least one recording surface, at least one head associated with the at least one recording surface for recording data on the at least...
6412062 Injection control mechanism for external events  
The present invention is a method and apparatus to inject an external event to a first pipeline stage in a pipeline chain. A target instruction address corresponding to an instruction is specified....
6397322 Integrated intrinsically safe input-output module  
A method and system for performing a task in an intrinsically safe environment using an intrinsically safe, integrated module located on the safe side to convey signals to and from a field device...
6389526 Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system  
A circuit and method is provided for selectively stalling interrupt requests originating devices coupled to a multiprocessor system. The multiprocessor system includes a plurality of circuit nodes...
6370606 System and method for simulating hardware interrupts in a multiprocessor computer system  
A technique for providing hardware interrupt simulation using the interprocessor interrupt mechanism of the local Advanced Programmable Interrupt Controller (APIC) on a Symmetric Multiprocessor...
6347378 Techniques and circuits for high yield improvements in programmable devices using redundant logic  
A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a...
6272618 System and method for handling interrupts in a multi-processor computer  
A system and method for handling system management interrupts in a multi-processor computer is disclosed. When the computer enters system management mode, the method uses the registers of each...
6243786 Apparatus and method for generating an interrupt prohibited zone in pipelined data processors  
In a preferred embodiment of the present invention an a method whereby a pipelined data processor with an embedded microinstruction sequencer can give special consideration to the interrupt of the...
6226753 Single chip integrated circuit with external bus interface  
A semiconductor integrated circuit for suppressing power consumption is provided. In the case where an internal signal should be monitored from outside the circuit, an output control circuit...
6223274 Power-and speed-efficient data storage/transfer architecture models and design methodologies for programmable or reusable multi-media processors  
A programmable processing engine and a method of operating the same is described, the processing engine including a customized processor, a flexible processor and a data store commonly sharable...
6223265 Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal  
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
6205556 Semiconductor integrated circuit device comprising a memory array and a processing circuit  
Herein disclosed is a data processing system having a memory packaged therein for realizing a large-scale and high-speed parallel distributed processing and, especially, a data processing system...
6175914 Processor including a combined parallel debug and trace port and a serial port  
A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace...
6175890 Device for efficiently handling interrupt request processes  
When an interrupt request signal is input, a microprocessor checks, upon termination of an instruction cycle being executed, whether the interrupt request is masked. If the interrupt request is not...
6088743 Processor receiving response request corresponding to access clock signal with buffer for external transfer synchronous to response request and internal transfer synchronous to operational clock  
A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated...
6085308 Protocol processor for the execution of a collection of instructions in a reduced number of operations  
Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor...
6058470 Specialized millicode instruction for translate and test  
A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set...
6055623 Specialized millicode instruction for editing functions  
A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set...
6055624 Millicode flags with specialized update and branch instructions  
A computer system having a pipelined computer processor, which executes a relatively simple instruction set in a hardware controlled execution unit and executes a relatively complex instruction set...
6052770 Asynchronous register  
A NULL convention asynchronous register regulates wavefronts of signals through a NULL convention sequential circuit. The asynchronous register receives a control signal from a downstream circuit...
6044456 Electronic system and method for maintaining synchronization of multiple front-end pipelines  
A system and method are described for maintaining synchronization of information propagating through multiple front-end pipelines operating in parallel. In general, these multiple front-end...
6029239 Configuring a communications system with a configurable data transfer architecture  
A communications system utilizes an embedded Digital Signal Processor (DSP), a DSP interface and memory architecture, a micro-controller interface, a DSP operating system (OS), a data flow model,...
6021483 PCI-to-PCI bridges with a timer register for storing a delayed transaction latency  
To improve the efficiency of delayed transactions in bus-to-bus bridge systems which include at least one interface to a PCI bus, a bridge system is disclosed including at least a primary interface...
5935236 Microcomputer capable of outputting pulses  
A microcomputer capable of outputting pulses in which an arithmetic processing unit outputs pulse control data according to the receiving of a trigger signal transferred from a trigger circuit, a...
5925115 Method and system for extending interrupt sources and implementing hardware based and software based prioritization of interrupts for an embedded processor  
The present invention comprises and interrupt controller for use with a programmable digital processor system. The interrupt controller of the present invention includes a plurality of interrupt...
5913071 Scalar interrupt-acknowledgement system that responds to a plurality of events with a single interrupt signal  
A peripheral device and a host device implement a scalar interrupt-acknowledgement system. The peripheral device detects events and increments an unprocessed counter in response to each detected...
5901309 Method for improved interrupt handling within a microprocessor  
A method and apparatus for processing interrupts received by a processor during the processing of an instruction set by a processing pipeline is disclosed. Initially, an interrupt associated with...
5875482 Method and apparatus for programmable chip select negation in a data processing system  
A data processing system (20) having programmable chip select signal negation. A user programmable "NEGATE EARLY" value generates a chip select negation one bus cycle before the end of a...
5848283 Method and system for efficient maintenance of data coherency in a multiprocessor system utilizing cache synchronization  
A method and system are efficiently maintaining data coherency in a multiprocessor data processing system having multiple processors coupled together via common bus. Each time an attempted...
5812868 Method and apparatus for selecting a register file in a data processing system  
A data processing system selects between a general register file and an alternate register file during an operation such that resources of the data processor may be more flexibly mapped to a...
5805901 Structure and method for mapping interrupt requests in a high-speed CPU interconnect bus system  
A compressed I/O bus system for a general-purpose computer multiplexes 32 bit data and addresses on 32 of 42 dedicated parallel signal paths, and optimizes the bus structure by mapping bus requests...
5805912 Microprocessor arranged to synchronously access an external memory operating at a slower rate than the microproccessor  
A microprocessor is provided which executes synchronous accesses to an external memory whether the external memory is operating at the same frequency as the operating frequency of the...
Matches 1 - 50 out of 64 1 2 >