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8175853 |
Systems and methods for a combined matrix-vector and matrix transpose vector multiply for a block-sparse matrix
Systems and methods for combined matrix-vector and matrix-transpose vector multiply for block sparse matrices. Exemplary embodiments include a method of updating a simulation of physical objects in...
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8108652 |
Vector processing with high execution throughput
The claimed invention is an efficient and high-performance vector processor. Through minimizing the use of multiple banks of memory and/or multi-ported memory blocks to reduce implementation cost,...
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8073881 |
Methods and apparatus facilitating access to storage among multiple computers
Multiple computers in a cluster maintain respective sets of identifiers of neighbor computers in the cluster for each of multiple named resource. A combination of the respective sets of identifiers...
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7984273 |
System and method for using a mask register to track progress of gathering elements from memory
A system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for...
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7971036 |
Methods and apparatus for attaching application specific functions within an array processor
A multi-node video signal processor (VSPN) is describes that tightly couples multiple multi-cycle state machines (hardware assist units) to each processor and each memory in each node of an N node...
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7949853 |
Two dimensional addressing of a matrix-vector register array
A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B...
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7908460 |
Method and apparatus for obtaining a scalar value directly from a vector register
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a...
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7895379 |
Logic controller having hard-coded control logic and programmable override control store entries
Control logic of a node controller receives an input vector and produces an output vector. The control logic includes a plurality of tied control store entries including hard-coded logic to...
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7818539 |
System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values
A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output...
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7809931 |
Arrangement, system and method for vector permutation in single-instruction multiple-data mircoprocessors
A vector permutation system (100) for a single-instruction multiple-data microprocessor has a set of vector registers (110) which feed vectors to permutation logic (120) and then to a negate block...
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7793073 |
Method and apparatus for indirectly addressed vector load-add-store across multi-processors
A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented,...
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7793072 |
Vector execution unit to process a vector instruction by executing a first operation on a first set of operands and a second operation on a second set of operands
A microprocessor including an execution unit enabled to execute an asymmetric instruction, where the asymmetric instruction includes a set of operand fields and an operation code (opcode). The...
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7788471 |
Data processor and methods thereof
A system and method for performing vector arithmetic is disclosed. The method includes loading two operand vectors, each composed of a number of vector elements, into two storage locations. A...
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7743231 |
Fast sparse list walker
Provided are a method, information processing system, and computer readable medium for identifying active bits in a vector. The method comprises receiving a pointer associated with a vector of...
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7739480 |
Method and apparatus for obtaining a scalar value directly from a vector register
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a...
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7725678 |
Method and apparatus for producing an index vector for use in performing a vector permute operation
A method for generating a permutation index vector includes receiving a condition vector and performing an index generation function using the condition vector in order to generate the permutation...
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7610469 |
Vector transfer system for packing dis-contiguous vector elements together into a single bus transfer
A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the...
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7548248 |
Method and apparatus for image blending
Methods and apparatuses for blending two images using vector table look up operations. In one aspect of the invention, a method to blend two images includes: loading a vector of keys into a vector...
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7519797 |
Hierarchical multi-precision pipeline counters
An event occurring in a graphics pipeline is detected and counted at the location of its occurrence using an event detector and a local counter. The event count maintained by the local counter is...
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7516299 |
Splat copying GPR data to vector register elements by executing lvsr or lvsl and vector subtract instructions
A method for transferring data from a general purpose register (GPR) to a vector register (VR), the method including vectorially combining data in the VR from the GPR, by executing instructions of...
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7496731 |
Two dimensional addressing of a matrix-vector register array
A method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary...
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7467287 |
Method and apparatus for vector table look-up
Methods and apparatuses for performing vector table look-up using multiple look-up tables. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a...
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7421565 |
Method and apparatus for indirectly addressed vector load-add -store across multi-processors
A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented,...
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7404065 |
Flow optimization and prediction for VSSE memory operations
In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises...
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7366873 |
Indirectly addressed vector load-operate-store method and apparatus
A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented,...
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7353371 |
Circuit to extract nonadjacent bits from data packets
A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination...
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7350057 |
Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction
Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for...
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7315932 |
Data processing system having instruction specifiers for SIMD register operands and method thereof
Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of...
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7293258 |
Data processor and method for using a data processor with debug circuit
A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of...
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7254696 |
Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests
A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC...
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7219212 |
Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one...
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7216218 |
Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations
The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and...
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7206857 |
Method and apparatus for a network processor having an architecture that supports burst writes and/or reads
A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth...
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7200724 |
Two dimensional data access in a processor
A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second...
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7197625 |
Alignment and ordering of vector elements for single instruction multiple data processing
The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a...
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7111156 |
Method and apparatus for multi-thread accumulation buffering in a computation engine
A method and apparatus for enhancing flexibility of instruction ordering in a multi-thread processing system that performs multiply and accumulate operations is presented. A plurality of...
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7107435 |
System and method for using hardware assist functions to process multiple arbitrary sized data elements in a register
A system and method for processing multiple arbitrary sized data elements in a register. A method of the invention comprises the steps of: creating a mask register that defines a set of arbitrary...
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7100026 |
System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values
A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output...
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7093102 |
Code sequence for vector gather and scatter
Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required...
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7065413 |
Method for producing software for controlling mechanisms and technical systems
In a method for controlling mechanisms or technical systems, the mechanisms or technical systems to be controlled are stored in a controller with their states, and with associated signal formers of...
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7055018 |
Apparatus for parallel vector table look-up
Methods and apparatuses for performing simultaneous table look-up using multiple look-up tables. In one aspect of the invention, an execution unit in a microprocessor includes: look-up memory and a...
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7036112 |
Multi-mode specification-driven disassembler
One embodiment of the present invention provides a system that facilitates implementing multi-mode specification-driven disassembler. During operation, the disassembler receives a machine-code...
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7000099 |
Large table vectorized lookup by selecting entries of vectors resulting from permute operations on sub-tables
A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data...
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6963341 |
Fast and flexible scan conversion and matrix transpose in a SIMD processor
The present invention provides efficient ways to implement scan conversion and matrix transpose operations using vector multiplex operations in a SIMD processor. The present method provides a very...
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6954927 |
Hardware supported software pipelined loop prologue optimization
A method for optimizing a software pipelineable loop in a software code is provided. The loop comprises one or more pipelined stages and one or more loop operations. The method comprises evaluating...
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6931511 |
Parallel vector table look-up with replicated index element vector
Methods and apparatuses for looking up vectors in parallel using vector table look up operations. In one aspect of the invention, a method to look up a plurality of data items indexed by a vector...
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6924802 |
Efficient function interpolation using SIMD vector permute functionality
A system, method, and computer program product are provided for generating display data. The data processing system loads coefficient values corresponding to a behavior of a selected function in...
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6915411 |
SIMD processor with concurrent operation of vector pointer datapath and vector computation datapath
A digital signal processor (DSP) includes a SIMD-based organization wherein operations are executed on a plurality of single-instruction multiple data (SIMD) datapaths or stages connected in...
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6865517 |
Aggregation of sensory data for distributed decision-making
A method, apparatus and computer product that enables a processor associated with a node in a computer system having various nodes, the nodes having sensors which provide data, and the nodes being...
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6829696 |
Data processing system with register store/load utilizing data packing/unpacking
A data processing system (e.g., microprocessor 30) for packing register data while storing it to memory and unpacking data read from memory while loading it into registers using single processor...
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