Matches 1 - 50 out of 121 1 2 3 >
Match Document Document Title
7610469 Vector transfer system for packing dis-contiguous vector elements together into a single bus transfer  
A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the...
7548248 Method and apparatus for image blending  
Methods and apparatuses for blending two images using vector table look up operations. In one aspect of the invention, a method to blend two images includes: loading a vector of keys into a vector...
7519797 Hierarchical multi-precision pipeline counters  
An event occurring in a graphics pipeline is detected and counted at the location of its occurrence using an event detector and a local counter. The event count maintained by the local counter is...
7516299 Splat copying GPR data to vector register elements by executing lvsr or lvsl and vector subtract instructions  
A method for transferring data from a general purpose register (GPR) to a vector register (VR), the method including vectorially combining data in the VR from the GPR, by executing instructions of...
7496731 Two dimensional addressing of a matrix-vector register array  
A method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary...
7467287 Method and apparatus for vector table look-up  
Methods and apparatuses for performing vector table look-up using multiple look-up tables. In one aspect of the invention, a method for execution by a microprocessor in response to receiving a...
7421565 Method and apparatus for indirectly addressed vector load-add -store across multi-processors  
A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented,...
7404065 Flow optimization and prediction for VSSE memory operations  
In one embodiment, a method for flow optimization and prediction for vector streaming single instruction, multiple data (SIMD) extension (VSSE) memory operations is disclosed. The method comprises...
7366873 Indirectly addressed vector load-operate-store method and apparatus  
A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented,...
7353371 Circuit to extract nonadjacent bits from data packets  
A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination...
7350057 Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction  
Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for...
7315932 Data processing system having instruction specifiers for SIMD register operands and method thereof  
Various load and store instructions may be used to transfer multiple vector elements between registers in a register file and memory. A cnt parameter may be used to indicate a total number of...
7293258 Data processor and method for using a data processor with debug circuit  
A data processor has a debug circuit arranged to monitor whether operand data used for execution of a program meets a debug exception condition. The debug exception condition tests a two or more of...
7254696 Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests  
A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC...
7219212 Load/store operation of memory misaligned vector data using alignment register storing realigned data portion for combining with remaining portion  
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one...
7216218 Microprocessor with high speed memory integrated in load/store unit to efficiently perform scatter and gather operations  
The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and...
7206857 Method and apparatus for a network processor having an architecture that supports burst writes and/or reads  
A method is described that involves recognizing that an input queue state has reached a buffer's worth of information. The method also involves generating a first request to read a buffer's worth...
7200724 Two dimensional data access in a processor  
A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second...
7197625 Alignment and ordering of vector elements for single instruction multiple data processing  
The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a...
7111156 Method and apparatus for multi-thread accumulation buffering in a computation engine  
A method and apparatus for enhancing flexibility of instruction ordering in a multi-thread processing system that performs multiply and accumulate operations is presented. A plurality of...
7107435 System and method for using hardware assist functions to process multiple arbitrary sized data elements in a register  
A system and method for processing multiple arbitrary sized data elements in a register. A method of the invention comprises the steps of: creating a mask register that defines a set of arbitrary...
7100026 System and method for performing efficient conditional vector operations for data parallel architectures involving both input and conditional vector values  
A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output...
7093102 Code sequence for vector gather and scatter  
Gather and scatter operations are used when elements of a vector which may be operated on in parallel are not located at successive addresses in memory. Prior data processing systems required...
7080216 Data access in a processor  
A data processor comprising: a register memory comprising an array of memory cells extending in two dimensions, the cells being located on rows in the first dimension and columns in the second...
7065413 Method for producing software for controlling mechanisms and technical systems  
In a method for controlling mechanisms or technical systems, the mechanisms or technical systems to be controlled are stored in a controller with their states, and with associated signal formers of...
7055018 Apparatus for parallel vector table look-up  
Methods and apparatuses for performing simultaneous table look-up using multiple look-up tables. In one aspect of the invention, an execution unit in a microprocessor includes: look-up memory and a...
7036112 Multi-mode specification-driven disassembler  
One embodiment of the present invention provides a system that facilitates implementing multi-mode specification-driven disassembler. During operation, the disassembler receives a machine-code...
7000099 Large table vectorized lookup by selecting entries of vectors resulting from permute operations on sub-tables  
A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data...
6963341 Fast and flexible scan conversion and matrix transpose in a SIMD processor  
The present invention provides efficient ways to implement scan conversion and matrix transpose operations using vector multiplex operations in a SIMD processor. The present method provides a very...
6954927 Hardware supported software pipelined loop prologue optimization  
A method for optimizing a software pipelineable loop in a software code is provided. The loop comprises one or more pipelined stages and one or more loop operations. The method comprises evaluating...
6931511 Parallel vector table look-up with replicated index element vector  
Methods and apparatuses for looking up vectors in parallel using vector table look up operations. In one aspect of the invention, a method to look up a plurality of data items indexed by a vector...
6924802 Efficient function interpolation using SIMD vector permute functionality  
A system, method, and computer program product are provided for generating display data. The data processing system loads coefficient values corresponding to a behavior of a selected function in...
6915411 SIMD processor with concurrent operation of vector pointer datapath and vector computation datapath  
A digital signal processor (DSP) includes a SIMD-based organization wherein operations are executed on a plurality of single-instruction multiple data (SIMD) datapaths or stages connected in...
6865517 Aggregation of sensory data for distributed decision-making  
A method, apparatus and computer product that enables a processor associated with a node in a computer system having various nodes, the nodes having sensors which provide data, and the nodes being...
6829696 Data processing system with register store/load utilizing data packing/unpacking  
A data processing system (e.g., microprocessor 30 ) for packing register data while storing it to memory and unpacking data read from memory while loading it into registers using single processor...
6816960 Cache consistent control of subsequent overlapping memory access during specified vector scatter instruction execution  
A vector artchitecture processing unit according to the present invention comprises a vector scatter (VSC) address coincidence detection unit 3 that comprises registers in which an area start...
6813701 Method and apparatus for transferring vector data between memory and a register file  
A compiler and vector data transfer instructions for use in a vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. The compiler...
6795908 Method and apparatus for instruction execution in a data processing system  
A method for processing scalar and vector executions, where vector executions may be “true” vector operations, CVA, or pseudo-vector operations, PVA. All three types of executions are processed...
6789181 Safety net paradigm for managing two computer execution modes  
A method and computer for executing the method. A source program is translated into an object program, in a manner in which the translated object program has a different execution behavior than the...
6782470 Operand queues for streaming data: A processor register file extension  
The register file of a processor includes embedded operand queues. The configuration of the register file into registers and operand queues is defined dynamically by a computer program. The...
6751725 Methods and apparatuses to clear state for operation of a stack  
Methods and apparatuses to clear state for operation of a stack. According to one embodiment of the invention, a processor comprises a set of one or more storage areas and a decode unit. The set of...
6742106 Vector transfer system generating address error exception when vector to be transferred does not start and end on same memory page  
A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector data transfer instructions are posted to an instruction queue in the...
6728874 System and method for processing vectorized data  
A method and system for correctly processing both big endian and little endian vector data. If the vector has a little endian data order, each piece of data (such as a byte) within the vector is...
6701424 Method and apparatus for efficient loading and storing of vectors  
A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location...
6665774 Vector and scalar data cache for a vector multiprocessor  
A common scalar/vector data cache apparatus and method for a scalar/vector computer. One aspect of the present invention provides a computer system including a memory. The memory includes a...
6625720 System for posting vector synchronization instructions to vector instruction queue to separate vector instructions from different application programs  
A vector transfer unit for handling transfers of vector data between a memory and a data processor in a computer system. Vector instructions are used for transferring the vector data between memory...
6553474 Data processor changing an alignment of loaded data  
A data processor in which a read operation, including misaligned data as operand data, can be performed in a single cycle. An alignment buffer having a register to hold data stored at one address...
6530011 Method and apparatus for vector register with scalar values  
A method and an apparatus for implementing mixed scalar and vector values in a digital processing system. In one embodiment, a digital processing system, which contains processing unit and...
6446193 Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture  
A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second...
6401194 Execution unit for processing a data stream independently and in parallel  
A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic...
Matches 1 - 50 out of 121 1 2 3 >