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7617386 Scheduling thread upon ready signal set when port transfers data on trigger time activation  
A processor has an interface portion and an interior environment. The interface portion comprises: at least one port arranged to receive a current time value; a first register associated with the...
7613909 Resuming thread to service ready port transferring data externally at different clock rate than internal circuitry of a processor  
A processor has an interface portion and an internal environment. The interface portion comprises at least one port. The internal environment comprises an execution unit arranged to execute...
7587579 Processor core interface for providing external hardware modules with access to registers of the core and methods thereof  
A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to...
7577779 Method and system for a RFIC master  
Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device...
7515453 Integrated memory core and memory interface circuit  
A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit...
7409531 Integrated micro-controller and programmable device  
A single-IC subsystem controller for controlling electronic devices and subsystems within computer systems and other large electronic systems. The single-IC subsystem controller includes a...
7305540 Method and apparatus for data processing  
Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling...
7263627 System and method having strapping with override functions  
A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the...
7237092 Microprocessor circuit for portable data carriers and method for operating the circuit  
A microprocessor circuit includes a control unit, a memory for free programming with at least one program having functions, a stack for buffer-storing data, a register bank having at least one...
7171542 Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins  
A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are...
7126375 Floor plan for scalable multiple level tab oriented interconnect architecture  
A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the...
7076636 Data storage system having an improved memory circuit board configured to run scripts  
A data storage system includes a set of storage devices, a memory circuit board that includes a cache to temporarily store copies of data elements stored in the set of storage devices, and a...
7009422 Floor plan for scalable multiple level tab oriented interconnect architecture  
A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative,...
6988182 Method for upgrading firmware in an electronic device  
An improved method of upgrading the firmware of an electronic device is disclosed. The method is executed over a communications link. The method includes compression of a portion of the new...
6963829 Method and apparatus for interfacing a spectrum digital incorporated TMS470 evaluation board with a spectrum digital incorporated TMS320LC54X evaluation board  
A bridge board connects a TMS470 processor evaluation module and a TMS320C54XX processor evaluation module. The bridge board performs translation of signal formats on both of the boards and also...
6931513 Data converter with statistical domain output  
An integrated circuit having statistical processing capability. The integrated circuit has an input for receiving input data in a first data domain. A data converter is provided for converting...
6907514 Microcomputer and microcomputer system  
A microcomputer is provided with a data-transfer unit such as a DMA (direct memory access) controller for controlling a transfer of data through an external bus. Used in an access to an external...
6832194 Audio recognition peripheral system  
The present invention includes a novel audio recognition peripheral system and method. The audio recognition peripheral system comprises an audio recognition peripheral a programmable processor...
6826628 PCI-PCMCIA smart card reader  
A method and apparatus is disclosed for implementing an integrated video card and smart card reader. A single processor is used to perform both video and smart card reader functions. The processor...
6748507 Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory  
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
6697931 System and method for communicating information to and from a single chip computer system through an external communication port with translation circuitry  
There is disclosed a computer system including a microprocessor on a single integrated circuit chip comprising an on-chip CPU and a communication bus providing a parallel communication path between...
6675284 Integrated circuit with multiple processing cores  
An integrated circuit having a serial data input pin and a serial data output pin, on-chip functional circuitry comprising at least two processing cores, a data adaptor which is in communication...
6665700 Distributed-memory multiprocessor system utilizing plural multiprocessors with virtual storage space  
In a distributed-memory multiprocessor system in which a plurality of processors have their respective memories, some of the processors are placed in redundant execution of writing into a virtual...
6622181 Timing window elimination in self-modifying direct memory access processors  
A direct memory access function for servicing real-time events, ensures that any parameter reloads occur during times when the direct memory access channel is idle and guarantees completion before...
6594711 Method and apparatus for operating one or more caches in conjunction with direct memory access controller  
A data processing apparatus includes a data processor core having integral cache memory and local memory, and external memory interface and a direct memory access unit. The direct memory access...
6580288 Multi-property microprocessor with no additional logic overhead to shared pins  
The present invention is embodied in a system and method for sharing input and output pins between a plurality of separate logic circuits coexisting within a single microprocessor such that the...
6532533 Input/output system with mask register bit control of memory mapped access to individual input/output pins  
A processing device ( 10 ) provides general-purpose input/output pins ( 52 ) for use by software routines as needed. A data input register ( 54 ) has bits corresponding to each pin ( 52 ) for...
6502182 Digital signal processing device  
A digital signal processing device applicable to a signal processing system using a CPU is mainly configured by an external memory and a digital signal processor (i.e., DSP), which are connected...
6496740 Transfer controller with hub and ports architecture  
The transfer controller with hub and ports (TCHP) performs the task of communication throughout an entire system in a centralized function. A single hub ( 435 ) tied to multiple ports ( 440, 447,...
6449740 Conductive paths controllably coupling pad groups arranged along one edge to CPU and to EEPROM in test mode  
An EEPROM is incorporated in a single chip microcomputer for storing programmed instruction codes, and is tested before separation of a semiconductor wafer into semiconductor chips, wherein pads...
6446212 Processor having an extended operating voltage range  
A processing unit, preferably a RISC based microcontroller, is coupled to a processing unit voltage regulator. The processing unit voltage regulator is used for controlling an operating voltage of...
6425100 Snoopy test access port architecture for electronic circuits including embedded core with built-in test access port  
This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core...
6425071 Subsystem bridge of AMBA's ASB bus to peripheral component interconnect (PCI) bus  
A method and apparatus to bridge between the PCI bus and a RISC processor interface bus. In one embodiment, the present invention is a single-ASIC implementation rather than a design using multiple...
6415424 Multiprocessor system with a high performance integrated distributed switch (IDS) controller  
A data processing system having a modified processor chip and external components to the processor chip. The processor chip is interconnected to the external components via point-to-point bus...
6401191 System and method for remotely executing code  
There is disclosed a computer system comprising a microprocessor on a single integrated circuit chip connected to an external computer device. The chip has a CPU and a communication bus providing a...
6397325 Microcomputer with packet translation for event packets and memory access packets  
A computer system includes an address and data path interconnecting an on-chip CPU with a module and an external communication port, event request packets being generated by the CPU and the module...
6389527 Microprocessor allowing simultaneous instruction execution and DMA transfer  
The present invention comprises a LSU which executes instructions relating to load/store. The LSU includes a DCACHE which temporarily stores data read from and written to the external memory, an...
6378090 Hierarchical test access port architecture for electronic circuits including embedded core having built-in test access port  
This invention is a testing technique for an electronic circuit such as an integrated circuit. The electronic circuit includes a JTAG test access port and at least one testable embedded core...
6334181 DSP with wait state registers having at least two portions  
A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for...
6311264 Digital signal processor with wait state register  
A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for...
6266762 Information processing apparatus  
A general-use register set includes a plurality of registers in a central processing unit body. A register-bank memory has memory regions relevant to the plurality of registers and is connected to...
6263419 Integrated circuit with wait state registers  
A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for...
6263418 Process of operating a microprocessor to use wait state numbers  
A data processing device is used with peripheral devices having addresses and differing communication response periods. The data processing device includes a digital processor adapted for selecting...
6249860 System with wait state registers  
A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for...
6247111 System with wait state register  
A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for...
6240504 Process of operating a microprocessor to change wait states  
A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for...
6226736 Microprocessor configuration arrangement for selecting an external bus width  
A microprocessor circuit arrangement is capable of retrieving and executing program instructions from a program memory having one of multiple possible bit-widths using address signals. A...
6223265 Single-chip microcomputer synchronously controlling external synchronous memory responsive to memory clock signal and clock enable signal  
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
6216217 Data processor  
A data processor including: a CPU (1) for performing a wait operation upon input of a wait signal (10) to its wait terminal (9); a wait/wait cancel instruction setting register (11) to which the...
6205536 Combined Instruction and address caching system using independent buses  
A microprocessor and a data processor therefor which have separate data and instruction buses, and wherein a data address and an instruction address are output over a single address bus in a...
Matches 1 - 50 out of 170 1 2 3 4 >