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7620796 System and method for acceleration of streams of dependent instructions within a microprocessor  
A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a...
7617334 Data processing system, data processing method and program  
In the host, an IP issues CCW, and a CH encodes the CCW and a CCW chain by the encode program to create a code including the description of controlling a conditional branch with the DKC and...
7613109 Processing data for a TCP connection using an offload unit  
A method and apparatus for processing data received and transmitted on a TCP connection is described. An offload unit processes received data for which a special case does not exist, to produce...
7614056 Processor specific dispatching in a heterogeneous configuration  
An abstraction layer is comprised in the operating system that represents the particulars of the PPMs. The abstractions in the abstraction layer are differentiated from one another by parameters...
7600096 Coprocessor extension architecture built using a novel split-instruction transaction model  
A processor architecture supports an electrical interface for coupling the processor core to one or more coprocessor extension units executing computational instructions, with a split-instruction...
7594097 Microprocessor output ports and control of instructions provided therefrom  
A method and apparatus are provided for controlling instructions provided by a microprocessor output port to other execution units. A microprocessor pipeline of instructions is provided for each...
7590823 Method and system for handling an instruction not supported in a coprocessor formed using configurable logic  
Method of informing a processor that a coprocessor instruction is not executable by a coprocessor is described. The coprocessor, instantiated in configurable logic, is configured to execute a...
7590869 On-chip multi-core type tamper resistant microprocessor  
The on-chip multi-core type tamper resistant processor has a feature that, on the microprocessor package which has a plurality of instruction execution cores on an identical package and an...
7590822 Tracking an instruction through a processor pipeline  
Method and apparatus for indicating to a coprocessor when the coprocessor can update internal register content thereof without negative repercussion to a processor is described. A controller is...
7587577 Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content  
A system architecture including a co-processor and a memory switch resource is disclosed. The memory switch includes multiple memory blocks and switch circuitry for selectably coupling processing...
7577822 Parallel task operation in processor and reconfigurable coprocessor configured based on information in link list including termination information for synchronization  
A reconfigurable processor (VPU) is designed for a technical environment having a standard processor (CPU) which has, for example, a DSP, RISC, CISC processor or a (micro)controller. The VPU and...
7546483 Offloading RAID functions to a graphics coprocessor  
Systems and methods for using a graphics processor to perform RAID parity functions may improve disk access performance. A method is provided for configuring a graphics processor to perform XOR...
7539847 Stalling processor pipeline for synchronization with coprocessor reconfigured to accommodate higher frequency operation resulting in additional number of pipeline stages  
A processor system that includes a main processor, and a coprocessor connected to the main processor. If the number of instruction execution cycles of an extended instruction executed by the...
7533246 Application program execution enhancing instruction set generation for coprocessor and code conversion with marking for function call translation  
A method for automatically configuring a microprocessor architecture so that it is able to efficiently exploit instruction level parallelism in a particular application. Executable code for another...
7533238 Method for limiting the size of a local storage of a processor  
A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a...
7523449 System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture  
A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable...
7516302 Efficient use of co-processor in platform independent instruction machine by controlling result transfer and translation and transfer timing of subsequent instruction based on instruction type for result forwarding  
A data processing method for processing a sequence of platform independent instructions on a data processing apparatus comprising a CPU and at least one further processor is disclosed. The data...
7502910 Sideband scout thread processor for reducing latency associated with a main processor  
A sideband scout thread processing technique is provided. The sideband scout thread processing technique utilizes sideband information to identify a subset of processor instructions for execution...
7500083 Accelerated processing with scheduling to configured coprocessor for molecular data type by service and control coprocessor upon analysis of software code  
An accelerated processing system includes one or more conventional processors, one or more coprocessors, and high speed data links between the processors, coprocessors and memory. In an embodiment,...
7493470 Processor apparatus and methods optimized for control applications  
Apparatus and methods for real-time control using a data processor. In one aspect, the invention comprises an improved processor having one or more extension instructions (and associated supporting...
7493471 Coprocessor receiving renamed register identifier from master to complete an operation upon register data ready  
A method for synchronized renaming between a master processor and a coprocessor includes sending from the master processor an operation for execution by the coprocessor along with an identifier, at...
7490223 Dynamic resource allocation among master processors that require service from a coprocessor  
An apparatus and a method dynamically reassign resources in a coprocessor among master processors that require service from the coprocessor. The method includes each processor, in each processor...
7490222 High and low power dual CPU cardiograph data processing system with gathering an display  
An electronic data processing device with dual-CPU for processing and sensing information related to heart beatings of a human body includes the first CPU and the second CPU. The first CPU, which...
7490221 Synchronization between pipelines in a data processing apparatus utilizing a synchronization queue  
The technology described provides a technique for synchronization between pipelines in a data processing apparatus. The data processing apparatus comprises a main processor operable to execute a...
7487302 Service layer architecture for memory access system and method  
A memory subsystem includes a memory controller operable to generate first control signals according to a standard interface. A memory interface adapter is coupled to the memory controller and is...
7480786 Methods and cores using existing PLD processors to emulate processors having different instruction sets and bus protocols  
Methods and cores using an existing processor implemented in a Programmable Logic Device (PLD) to emulate a target processor, where the existing and target processors support different instruction...
7457890 Integrated multimedia system  
An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local...
7444637 Systems and methods for scheduling coprocessor resources in a computing system  
Systems and methods for scheduling coprocessing resources in a computing system are provided without redesigning the coprocessor. In various embodiments, a system of preemptive multitasking is...
7437535 Method and apparatus for issuing a command to store an instruction and load resultant data in a microcontroller  
This disclosure relates to communications among processors, coprocessors and memory. Specifically, a method and apparatus provide a single-cycle instruction (“store-and-load”) that stores a...
7430652 Devices for performing multiple independent hardware acceleration operations and methods for performing same  
Multiple hardware accelerators can be used to efficiently perform processes that would otherwise be performed by general purpose hardware running software. The software overhead and bus bandwidth...
7418574 Configuring a portion of a pipeline accelerator to generate pipeline date without a program instruction  
A peer-vector machine includes a host processor and a hardwired pipeline accelerator. The host processor executes a program, and, in response to the program, generates host data, and the pipeline...
7411187 Ion trap in a semiconductor chip  
A micrometer-scale ion trap, fabricated on a monolithic chip using semiconductor micro-electromechanical systems (MEMS) technology. A single 111Cd+ ion is confined, laser cooled, and the heating...
7409251 Method and system for writing NV memories in a controller architecture, corresponding computer program product and computer-readable storage medium  
The invention describes a method and an arrangement for writing to NV memories in a controller architecture, together with a corresponding computer program product and a corresponding...
7406559 In-circuit programming architecture with processor, delegable flash controller, and code generator  
An architecture for an integrated circuit with in-circuit programming allows real-time modification of the in-circuit programming code and other code stored on the chip. The architecture utilizes a...
7398368 Atomic operation involving processors with different memory transfer operation sizes  
Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that...
7395409 Split embedded DRAM processor  
A processing architecture includes a first CPU core portion coupled to a second embedded dynamic random access memory (DRAM) portion. These architectural components jointly implement a single...
7395410 Processor system with an improved instruction decode control unit that controls data transfer between processor and coprocessor  
A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an...
7392524 Method, system, and storage medium for managing computer processing functions  
Exemplary embodiments include a method, system, and storage medium for managing computer processing functions in a multi-processor computer environment that includes a standard logical processor...
7386704 Pipeline accelerator including pipeline circuits in communication via a bus, and related system and method  
A pipeline accelerator includes a bus and a plurality of pipeline units, each unit coupled to the bus and including at least one respective hardwired-pipeline circuit. By including a plurality of...
7386705 Method for allocating processor resources and system for encrypting data  
An apparatus for calculating and encryption of data has a multistage processing array and a plurality of registers. Each register has a status bit which indicates a “go” or “done” condition...
7383424 Computer architecture containing processor and decoupled coprocessor  
A computer system comprises a first processor 1 and a second processor 2 for use as a coprocessor to the first processor 1 . The system has a main memory 3 . The system also has a decoupling...
7379418 Method for ensuring system serialization (quiesce) in a multi-processor environment  
A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one...
7376812 Vector co-processor for configurable and extensible processor architecture  
A processor can achieve high code density while allowing higher performance than existing architectures, particularly for Digital Signal Processing (DSP) applications. In accordance with one...
7373488 Processing for associated data size saturation flag history stored in SIMD coprocessor register using mask and test values  
A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information. A first coprocessor instruction has a first format identifying a...
7370123 Information processing apparatus  
A descriptor queue composed of descriptors containing input address information that represents an address for storing data to be processed and output address information that represents an address...
7363473 System for dynamic service provisioning  
Disclosed is a network processor configured to provide for dynamic service provisioning. A global connector defines a topology of packet processing functions that can be dynamically ordered to...
7356670 Data processing system  
A multiprocessor data processing system is described wherein the processors communicate to each other via a shared memory. Each of the processors comprises an administration unit ( 18 a ) and a...
7355601 System and method for transfer of data between processors using a locked set, head and tail pointers  
A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task...
7356676 Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register  
A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the...
7350055 Tightly coupled accelerator  
An accelerator 120 is tightly coupled to the normal execution unit 110 . The operand store, which could be a register file 130 , a stack based operand store or other operand store is shared by...
Matches 1 - 50 out of 299 1 2 3 4 5 6 >