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7613858 |
Implementing signal processing cores as application specific processors
Methods and apparatus are provided for efficiently implementing signal processing cores as application specific processors. A signal processing core, such as a Fast Fourier Transform (FFT) core or...
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7606943 |
Adaptable datapath for a digital processing system
The present invention includes a adaptable high-performance node (RXN) with several features that enable it to provide high performance along with adaptability. A preferred embodiment of the RXN...
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RE40942 |
Integrated digital signal processor/general purpose CPU with shared internal memory
An integrated data processing platform for processing a digital signal that includes a general purpose processor and a digital signal processor (DSP) module. The DSP module recovers digital data...
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7596144 |
System-on-a-chip (SoC) device with integrated support for ethernet, TCP, iSCSI, RDMA, and network application acceleration
Certain aspects of a method and system for a system-on-a-chip (SoC) device with integrated support for Ethernet, TCP, iSCSI, RDMA, and network application acceleration are provided. Aspects of the...
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7558944 |
Microcomputer
A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6 , and made accessible in parallel by third buses XAB and XDB and second buses...
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7533238 |
Method for limiting the size of a local storage of a processor
A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a...
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7519754 |
Hard disk drive cache memory and playback device
A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function...
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7480786 |
Methods and cores using existing PLD processors to emulate processors having different instruction sets and bus protocols
Methods and cores using an existing processor implemented in a Programmable Logic Device (PLD) to emulate a target processor, where the existing and target processors support different instruction...
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7475182 |
System-on-a-chip mixed bus architecture
A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could...
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7412588 |
Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus
A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the...
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7409251 |
Method and system for writing NV memories in a controller architecture, corresponding computer program product and computer-readable storage medium
The invention describes a method and an arrangement for writing to NV memories in a controller architecture, together with a corresponding computer program product and a corresponding...
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7353362 |
Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus
A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated...
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7305540 |
Method and apparatus for data processing
Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling...
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7243181 |
Signal bus arrangement
In a two-dimensional layout, the bus signal lines are arranged such that adjacent signal lines are of different buses. The different buses transmit signals changed at different timings. The signal...
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7231464 |
Management system for multimodule multiprocessor machines
The present invention relates to a global management system for a multimodule, multiprocessor machine (PK). The system is characterized in that it comprises an independent module (SM) dedicated to...
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7200735 |
High-performance hybrid processor with configurable execution units
A new general method for building hybrid processors achieves higher performance in applications by allowing more powerful, tightly-coupled instruction set extensions to be implemented in...
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7142443 |
Reduced data line pre-fetch scheme
A memory device for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper flip-flops...
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7133954 |
Data bus system for micro controller
Provided is a data bus system for a micro controller which has an input/output (I/O) unit, a central processing unit (CPU), an internal memory unit, and a peripheral circuitry. The data bus system...
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7111155 |
Digital signal processor computation core with input operand selection from operand bus for dual operations
A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a...
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7110830 |
Microprocessor system and method for protecting the system from the exchange of modules
A microprocessor system includes a plurality of modules, among them a microprocessor and at least one storage module for storing the code and/or data for the microprocessor. Stored, in a...
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7103753 |
Backplane system having high-density electrical connectors
A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by...
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7035906 |
Global network computers
This invention generally relates to one or more computer networks having computers like personal computers or network servers with microprocessors linked by broadband transmission means and having...
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7007154 |
Method and apparatus for interfacing a processor to a coprocessor
A processor ( 12 ) to coprocessor ( 14 ) interface supporting multiple coprocessors ( 14, 16 ) utilizes compiler generatable software type function call and return, instruction execute, and...
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6990566 |
Multi-channel bi-directional bus network with direction sideband bit for multiple context processing elements
A method and an apparatus for configuration of multiple context processing elements (MCPEs) are described. The method and an apparatus is capable of selectively transmitting data over a...
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6963965 |
Instruction-programmable processor with instruction loop cache
An instruction-programmable processor, such as a digital signal processor, having a level one program cache memory and instruction buffer subsystem, is disclosed. The subsystem includes a loop...
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6950898 |
Data amplifier having reduced data lines and/or higher data rates
A data amplifier configured to allow for fewer data lines and/or increased processing speeds. Specifically, multiple helper flip-flops are used to prefetch data in a data amplifier. The helper...
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6918025 |
IC with wait state registers
A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for...
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6898657 |
Autonomous signal processing resource for selective series processing of data in transit on communications paths in multi-processor arrangements
A multi-processor arrangement having an interprocessor communication path between each of every possible pair of processors, in addition to I/O paths to and from the arrangement, having signal...
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6871247 |
Mechanism for supporting self-modifying code in a harvard architecture digital signal processor and method of operation thereof
For use in a processor having separate instruction and data buses, separate instruction and data memories and separate instruction and data units, a mechanism for, and method of, supporting...
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6826674 |
Program product and data processor
In the present invention, an input and/or output interface of at least one of a plurality of processing units forming a data processing system is designated independently of timing of execution of...
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6820143 |
On-chip data transfer in multi-processor system
A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor....
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6816750 |
System-on-a-chip
A system 100 fabricated on a single integrated circuit chip includes a microprocessor 101 operating from a high speed bus 102 and a peripheral bus 103 operating in conjunction with high...
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6785743 |
Template data transfer coprocessor
The template data transfer coprocessor (TDTP) offloads block data transfer operations from a mediaprocessor. A uni-block template, program-guided template, an indirect template and queue-based...
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6760870 |
Algorithm for resynchronizing a bit-sliced crossbar
A data switch is configured to communicate data messages in the form of multibit data unit segmented into a plurality of multibit data subunits. The data switch includes at least two separate,...
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6757809 |
Data processor having 2n bits width data bus for context switching functions
A data processor being provided with a data register having a double width of the width of a general purpose register for inputting/outputting data with respect to the operand access unit, and a...
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6754763 |
Multi-board connection system for use in electronic design automation
A high fan-out hub array system and method is provided. The system includes at least one hub that contains user logic that receive signals from various chips and boards, and which quickly...
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6748507 |
Single-chip microcomputer with integral clock generating unit providing clock signals to CPU, internal circuit modules and synchronously controlling external dynamic memory
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
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6735683 |
Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
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6732203 |
Selectively multiplexing memory coupling global bus data bits to narrower functional unit coupling local bus
In one embodiment, a bus multiplexer is between a memory and a functional unit of the integrated circuit. An input of the bus multiplexer couples to a global bus having a bit width. A local bus...
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6715042 |
Systems and methods for multiport memory access in a multimaster environment
A multiprocessor digital amplifier system is disclosed. A first processor is configured to decode a digital signal from a digital signal source. A second processor configured to provide control...
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6704828 |
System and method for implementing data pre-fetch having reduced data lines and/or higher data rates
A method and apparatus for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper...
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6675283 |
Hierarchical connection of plurality of functional units with faster neighbor first level and slower distant second level connections
A device for a hierarchical connection of a plurality of functional units in a processor comprises a first connector with at least two inputs and an output, which is adapted for connecting one of...
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6658550 |
Pipelined asynchronous processing
An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to...
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6615341 |
Multiple-data bus architecture for a digital signal processor using variable-length instruction set with single instruction simultaneous control
A digital signal processor (DSP) employs a variable-length instruction set. A portion of the variable-length instructions may be stored in adjacent locations within memory space with the beginning...
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6574726 |
Modular architecture for high bandwidth computers
A computer system architecture in which functionally compatible electronic components are located on modular printed circuit boards. Thus, a type of processor used by the system can be changed by...
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6564242 |
Distributed automation system
A distributed automation system comprising a programmable logic controller connected to programmable logic controllers equipped with a host unit and couplers communicating with the host unit...
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6516402 |
Information processing apparatus with parallel accumulation capability
An initial value of read address is set in a first initial address register; an initial value of write address is set in a second initial address register; and the number of data to be accumulated...
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6505291 |
Processor having a datapath and control logic constituted with basis execution blocks
A processor is provided with a datapath and control logic, where the datapath and/or the control logic are constituted with basis execution blocks (BEB). Each BEB includes an addressable storage...
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6502181 |
Method and apparatus for an enhanced processor
A controller for executing instructions has one the order of five addressing modes and can allow executing of processes concurrently in multiple modes. A specific embodiment can effectively run...
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6496920 |
Digital signal processor having multiple access registers
A method and circuit for digital signal processing. The disclosed method and circuit uses a variable length instruction set. A portion of the variable length instructions may be stored in adjacent...
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