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9026239 APC model extension using existing APC models  
A method of extending advanced process control (APC) models includes constructing an APC model table including APC model parameters of a plurality of products and a plurality of work stations. The...
9015504 Managing power of thread pipelines according to clock frequency and voltage specified in thread registers  
A multi-threaded microprocessor for processing instructions in threads, including, in one embodiment, (1) at least one processor pipeline for the instructions; (2) a storage for a thread power...
RE45487 Processor having execution core sections operating at different clock rates  
A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations...
8996278 Control device for internal combustion engine  
In a control device for an internal combustion engine, which includes control unit that has a processor with a plurality of cores and that computes various tasks associated with operation of the...
8996895 Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates  
A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important...
8972995 Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads  
A method, apparatus, and system in which an integrated circuit comprises an initiator Intellectual Property (IP) core, a target IP core, an interconnect, and a tag and thread logic. The target IP...
8930635 Page invalidation processing with setting of storage key to predefined value  
Processing within a multiprocessor computer system is facilitated by: setting, in association with invalidate page table entry processing, a storage key at a matching location in central storage...
8929376 Flow control using a local event ring in an island-based network flow processor  
An island-based network flow processor (IB-NFP) integrated circuit includes islands organized in rows. A configurable mesh event bus extends through the islands and is configured to form a local...
8930676 Master core discovering enabled cores in microprocessor comprising plural multi-core dies  
A core configuration discovery method and corresponding microprocessor are provided that does not rely on off-core logic or queries by system BIOS. Reset microcode is provided in the...
8886917 Switching to core executing OS like codes upon system call reading greater than predetermined amount of data  
A multi-core processor includes at least one first core and at least one second core. The first core is optimized to run applications, and the second core is optimized to meet the computing...
8880753 Vehicle electronic controller for automatically switching between a port being suspended based on a mode of an internal oscillation circuit  
Some embodiments relate to a vehicle electronic controller having a microcomputer and a port expansion element, with reduced power consumption and radio noise. An MCU (microcomputer) performs...
8880485 Systems and methods to facilitate multi-threaded data retrieval  
According to some embodiments, a data source is accessed from which data will be retrieved via a plurality of processing threads. The data source may have, for example, a plurality of records with...
8874893 Effect translation and assessment among microarchitecture components  
Awareness of the relationships among the operating parameters for an individual core and among cores allows dynamic and intelligent management of the multi-core system. The relationships among...
8868941 Apparatus and methods for an interconnect power manager  
An interconnect-power-manager (IPM) cooperates and communicates signals with an integrated-circuit-system-power-manager (SPM) in the integrated-circuit. The interconnect network (IN) is...
8868848 Sharing virtual memory-based multi-version data between the heterogenous processors of a computer platform  
A computer system may comprise a computer platform and input-output devices. The computer platform may include a plurality of heterogeneous processors comprising a central processing unit (CPU)...
8862917 Dynamic sleep for multicore computing devices  
The aspects enable a multi-core processor or system on chip to determine a low power configuration that provides the most system power savings by placing selected resources in a low power mode...
8838900 Atomic-operation coalescing technique in multi-chip systems  
A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify...
8819396 Parallel processing using plural processing modules when processing time including parallel control overhead time is determined to be less than serial processing time  
A data processing apparatus includes an output unit. The output unit determines, when parallel control is performed in a data processor created in the data processing apparatus so that plural...
8806251 Image forming apparatus operating in normal operation mode or power save operation mode utilizing two processors  
An electric device is capable of operating in a normal operation mode and a power save operation mode. The electric device includes a first processor for processing information input externally in...
8799687 Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup rates  
A processor may include power management techniques to, dynamically, chose an optimal C-state for the processing core. The measurement of real workloads on the OSes exhibit two important...
8780120 GPU self throttling  
Techniques for GPU self throttling are described. In one or more embodiments, timing information for GPU frame processing is obtained using a timeline for the GPU. This may occur by inserting...
8726295 Network on chip with an I/O accelerator  
Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a...
8719552 Cache collaboration method, apparatus, and system  
A cache collaboration method includes obtaining, by an upper-layer cache node, bandwidth utilization rates of a backbone port and an edge port of the upper-layer cache node respectively, related...
8707062 Method and apparatus for powered off processor core mode  
For one disclosed embodiment, a processor comprises a first processor core, a second processor core, and a cache memory. The first processor core is to save a state of the first processor core and...
8701119 Parsing XML in software on CPU with multiple execution units  
An improved method for parsing XML data or NVP data in software is disclosed. The method takes advantage of some modern processors' architecture which has multiple execution units. The multiple...
8683474 Accounting apparatus and method for SMT processor  
In an accounting apparatus, a conflict determination unit determines whether or not the accounting mode is in a conflict state where a process is executing in another logical CPU and stores the...
8671293 Multi-core system energy consumption optimization  
Techniques described herein generally relate to optimizing energy consumption in a computer system. In some examples an energy usage benchmark can be determined for a system component of the...
8634302 Apparatus for multi-cell support in a network  
An apparatus for providing multi-cell support in a telecommunications network is described. The apparatus includes a modem board and a multi-core processor having a plurality of processor cores...
8635620 Hardware device for processing the tasks of an algorithm in parallel  
A hardware device for concurrently processing a fixed set of predetermined tasks associated with an algorithm which includes a number of processes, some of the processes being dependent on binary...
8615647 Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state  
Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a...
8610725 Framework for dynamic configuration of hardware resources  
Among other things, dynamically selecting or configuring one or more hardware resources to render a particular display data includes obtaining a request for rendering display data. The request...
8612726 Multi-cycle programmable processor with FSM implemented controller selectively altering functional units datapaths based on instruction type  
The multi-cycle programmable processor emulates the features of a conventional microprocessor. Processor hardware functional units include a program counter (instruction pointer), an arithmetic...
8566570 Distributed multi-core memory initialization  
In a system having a plurality of processing nodes, a control node divides a task into a plurality of sub-tasks, and assigns the sub-tasks to one or more additional processing nodes which execute...
8561164 Computers and microchips with a side protected by an internal hardware firewall and an unprotected side connected to a network  
A computer or microchip including one or more microprocessors or processing units, at least one network communication component, and an internal hardware firewall. located on a microchip and...
8555032 Microcontroller programmable system on a chip with programmable interconnect  
Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable...
8554007 Image processing apparatus, image processing method, and computer-readable storage medium for computer program  
An image processing apparatus includes a storage that stores, therein, edge position data indicating the position of a first edge image that represents a first edge of a first object image...
8549261 Parallel computing apparatus and parallel computing method  
Computational unit area selecting units, each of which is provided in individual multiple cores, sequentially select uncomputed computational unit areas in a computational area. Computing units,...
8543860 Multi-core clocking system with interlocked ‘anti-freeze’ mechanism  
A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock...
8533716 Resource management in a multicore architecture  
A method and apparatus for resource management in a multicore processor is disclosed. A system management controller (130) provides omnipresent scheduling, synchronization, load balancing, and...
RE44494 Processor having execution core sections operating at different clock rates  
A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations...
8522254 Programmable integrated processor blocks  
An integrated processor block of the network on a chip is programmable to perform a first function. The integrated processor block includes an inbox to receive incoming packets from other...
8510336 Transactional file system  
A transactional file system wherein multiple file system operations may be performed as a transaction. An application specifies that file system-related operations are to be handled as a...
8499182 Semiconductor device and data processing system  
A semiconductor device has reduced power consumption and processing time associated with the release of a low power consumption state set by a central processing unit thereof. The semiconductor...
8473906 Systems and methods for parallel distributed programming  
The present invention relates generally to computer programming, and more particularly to, systems and methods for parallel distributed programming. Generally, a parallel distributed program is...
8473681 Atomic-operation coalescing technique in multi-chip systems  
A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify...
8438578 Network on chip with an I/O accelerator  
Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a...
8433747 Graphics remoting architecture  
Systems and methods to implement a graphics remoting architecture for rendering graphics images at remote clients are disclosed. In one implementation, when a D3D application hosted on a remote...
8429441 Operating processor below maximum turbo mode frequency by sending higher than actual current amount signal to monitor  
A method, computer program product and system for controlling the maximum turbo mode of a processor in a turbo boost state. The method comprises limiting a maximum turbo mode available to the...
8412916 Computing system having CPU and bridge operating using CPU frequency  
An integrated circuit also referred to as an integrated computing system has a single substrate that has either deposited thereon or etched thereon, a central processing unit, a north bridge, a...
8379819 Indexing recordings of telephony sessions  
Improved indexing of telephony sessions is achieved by: (a) receiving, during the recording of the telephony session or during a playback of the recording, an indication including parameters which...