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7606960 |
Apparatus for adjusting a clock frequency of a variable speed bus
An embodiment involves throttling a bus frequency based upon incoming arbitration requests from units or devices coupled to a bus. Arbitration circuitry monitors request rates from each requestor...
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7595644 |
Power-over-ethernet isolation loss detector
An AC generator has a first terminal coupled through an Isolation Loss Detect (ILD) capacitor to the positive bus of a Power-Over-Ethernet (POE) system, and has a second terminal coupled through...
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7590869 |
On-chip multi-core type tamper resistant microprocessor
The on-chip multi-core type tamper resistant processor has a feature that, on the microprocessor package which has a plurality of instruction execution cores on an identical package and an...
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7583673 |
Network processor for forwarding packets in an IP network
A network processor, including: a programmable Application Specific Integrated Circuit (ASIC) module, with one or more main forwarding hardware pipelines for a main forwarding upon packet; a...
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7571284 |
Out-of-order memory transactions in a fine-grain multithreaded/multi-core processor
A method and apparatus for implementing out-of-order memory transactions in a multithreaded, multicore processor. In the present invention, circular queue comprising a plurality of queue buffers is...
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7564865 |
Weight factor based allocation of time slot to use link in connection path in network on chip IC
An integrated circuit comprising a plurality of processing modules (M, S; IP) and a network (N) arranged for coupling said modules (M, S; IP) is provided. Said integrated circuit further comprises...
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7553030 |
Fan unit and optical apparatus
A projector includes a fan unit having a fan, supporting members functioning as a supporting base of the fan, and at least one resilient member operatively connected to the fan. The supporting...
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7552312 |
Identifying messaging completion in a parallel computer by checking for change in message received and transmitted count at each node
Methods, parallel computers, and products are provided for identifying messaging completion on a parallel computer. The parallel computer includes a plurality of compute nodes, the compute nodes...
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7533382 |
Hyperprocessor
A hyperprocessor includes a control processor controlling tasks executed by a plurality of processor cores, each of which may include multiple execution units, or special hardware units. The...
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7533248 |
Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor
A multithreaded processor including a shared functional unit. In one embodiment, the multithreaded processor includes a functional unit coupled to a multithreaded instruction source that may...
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7533245 |
Hardware assisted pruned inverted index component
An optimized document-indexing device is based on a pruned inverted index structure mapped to hardware. The device can be accommodated on a single chip and can be reprogrammed to accommodate index...
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7533238 |
Method for limiting the size of a local storage of a processor
A method for limiting the size of a local storage of a processor is provided. A facility is provided in association with a processor for setting a local storage size limit. This facility is a...
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7525548 |
Video processing with multiple graphical processing units
One embodiment of a video processor includes a first media processing device coupled to a first memory and a second media processing device coupled to a second memory. The second media processing...
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7512836 |
Fast backup of compute nodes in failing midplane by copying to nodes in backup midplane via link chips operating in pass through and normal modes in massively parallel computing system
A method and apparatus for fast backup of a set of compute nodes to save the state of the software in a parallel computer system. A fast backup mechanism in the service node of the computer system...
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7502031 |
Automatic component interface creator
A cross-platform interface tool provides a common interface for any hardware or software component having some advertising mechanism listing its features, input, and output requirements. The...
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7490220 |
Multi-cluster processor operating only select number of clusters during each phase based on program statistic monitored at predetermined intervals
In a processor having multiple clusters which operate in parallel, the number of clusters in use can be varied dynamically. At the start of each program phase, the configuration option for an...
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7480786 |
Methods and cores using existing PLD processors to emulate processors having different instruction sets and bus protocols
Methods and cores using an existing processor implemented in a Programmable Logic Device (PLD) to emulate a target processor, where the existing and target processors support different instruction...
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7478032 |
Method and system for selecting compatible processors to add to a multiprocessor computer
A method and system for using processor compatibility information to select a compatible processor for addition to a multiprocessor computer. A software program is executed on the multiprocessor...
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7457938 |
Staggered execution stack for vector processing
In one embodiment, the present invention includes a method for executing an operation on low order portions of first and second source operands using a first execution stack of a processor and...
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7457890 |
Integrated multimedia system
An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local...
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7457886 |
System and method for input/output scheduling
A system and method for Input/Output scheduling are described herein. In one embodiment, the method includes installing a plurality of Input/Output (I/O) schedulers to schedule I/O requests for a...
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7456765 |
Systems and methods for clock mode determination utilizing master clock frequency measurements
A system for determining a data converter clock operating mode includes measurement circuitry which measures a master clock frequency of a master clock signal and a frequency ratio between a...
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7426722 |
Program code conversion for program code referring to variable size registers
A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine...
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7415595 |
Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory
A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable...
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7412588 |
Network processor system on chip with bridge coupling protocol converting multiprocessor macro core local bus to peripheral interfaces coupled system bus
A network processor includes a system-onchip (SoC) macro core and functions as a single chip protocol converter that receives packets generating according to a first protocol type and processes the...
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7409680 |
Program code conversion for a register-based program code
A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine...
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7409251 |
Method and system for writing NV memories in a controller architecture, corresponding computer program product and computer-readable storage medium
The invention describes a method and an arrangement for writing to NV memories in a controller architecture, together with a corresponding computer program product and a corresponding...
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7406584 |
IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability
Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and...
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7389391 |
Memory disposition methods and systems
A memory disposition system, comprising a first memory device and a second memory device. First and second memory devices are provided to a system, such as an embedded system. The first and the...
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7380037 |
Data transmitter between external device and working memory
A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU...
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7379418 |
Method for ensuring system serialization (quiesce) in a multi-processor environment
A method of ensuring system serialization in a multiprocessor multi-nodal environment is used to force all processors in a multiprocessor environment to temporarily suspend operations while one...
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7363625 |
Method for changing a thread priority in a simultaneous multithread processor
An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in...
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7363474 |
Method and apparatus for suspending execution of a thread until a specified memory access occurs
Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A...
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7360008 |
Enforcing global ordering through a caching bridge in a multicore multiprocessor system
The present invention presents an efficient way to implement global ordering between a system interconnect and internal core interfaces in a MCMP system. In particular, snooping transactions on the...
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7353362 |
Multiprocessor subsystem in SoC with bridge between processor clusters interconnetion and SoC system bus
A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated...
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7346900 |
Register-based program code conversion
A method of dynamic real time translation of first program code written for a first programmable machine into second program code (target code) for running on a second programmable machine...
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7302554 |
Methods and apparatus for multi-processor pipeline parallelism
A processor is provided which has a modular organization including at least one local store operable to store data and instructions for execution, at least one functional unit operable to execute...
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7302549 |
Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access
A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method...
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7302548 |
System and method for communicating in a multi-processor environment
A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination...
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7302532 |
Central processing unit
A central processing unit having: (A) a microprocessor; (B) a main memory; (C) a microprocessor interface. The interface includes: a semiconductor integrated circuit having formed therein: (i) a...
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7299342 |
Complex vector executing clustered SIMD micro-architecture DSP with accelerator coupled complex ALU paths each further including short multiplier/accumulator using two's complement
A programmable digital signal processor including a clustered SIMD microarchitecture includes a plurality of accelerator units, a processor core and a complex computing unit. Each of the...
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7293159 |
Coupling GP processor with reserved instruction interface via coprocessor port with operation data flow to application specific ISA processor with translation pre-decoder
Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute...
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7291891 |
In-solid nuclear spin quantum calculation device
A voltage is applied across gate electrodes ( 103 A) and ( 103 B) in a two-dimensional electronic system ( 101 ) placed under a magnetic field, and the polarity of an electric current passed...
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7263627 |
System and method having strapping with override functions
A system and method allow for overriding of a strapping option. A strapping signal places a device (e.g., a processor) in first state or mode (e.g., client or master). An override system places the...
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7263565 |
Bus system and integrated circuit having an address monitor unit
A bus system for handling changes in an access address range of a subject-of-access or a bus master is disclosed. The bus system can have an address monitor unit including a table which is shared...
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7243212 |
Processor-controller interface for non-lock step operation
Method and apparatus for non-lock-step operation between a processor and a controller is described. An instruction is provided from the processor to the controller. A busy signal is provided from...
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7239635 |
Method and apparatus for implementing alterations on multiple concurrent frames
A method and apparatus are provided for implementing frame header alterations on multiple concurrent frames. Each of a plurality of frame data alteration engines includes a pair of a command...
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7216213 |
Method of analyzing data utilizing queue entry
A processor having a limited amount of local memory for storing code and/or data utilizes a program stored in external memory. The program stored in external memory is configured into blocks which...
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7209988 |
Management of the freezing of a functional module in a system on a chip
An electronic system comprises an initiator module and a target module addressable by the initiator module. The initiator module is activated by edges of an activation signal generated from a first...
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7206894 |
Microcomputer application system, microcomputer, signal processing system and signal processing LSI
An external ROM stores a control program PG for controlling a microcomputer. An MPU executes copy processing to copy a high-speed processing part PGM 1 stored in the external ROM to a high-speed...
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