Matches 151 - 200 out of 387 < 1 2 3 4 5 6 7 8 >
Match Document Document Title
6412061 Dynamic pipelines with reusable logic elements controlled by a set of multiplexers for pipeline stage selection  
A method of dynamically adjusting a multiple stage pipeline to execute one of a set of instructions, wherein each stage has a latency and performs a selected data operation. An instruction to be...
6393555 Rapid execution of FCMOV following FCOMI by storing comparison result in temporary register in floating point unit  
A microprocessor with a floating point unit configured to rapidly execute floating point compare (FCOMI) type instructions that are followed by floating point conditional move (FCMOV) type...
6389527 Microprocessor allowing simultaneous instruction execution and DMA transfer  
The present invention comprises a LSU which executes instructions relating to load/store. The LSU includes a DCACHE which temporarily stores data read from and written to the external memory, an...
6381688 Serial port for a hose adapter integrated circuit using a single terminal  
A host adapter integrated circuit that contains data transfer modules has a serial port that uses a single serial port pin to communicate with a slave serial port input-output integrated circuit...
6378060 System to implement a cross-bar switch of a broadband processor  
The present invention provides a cross-bar circuit that implements a switch of a broadband processor. In an exemplary embodiment, the present invention provides a cross-bar circuit that, in...
6370635 Dual ROM microprogrammable microcontroller and universal serial bus microcontroller development system  
A microprogrammable microprocessor that stores microprogramming instruction sets in a dual ROM configuration enhancing reusability of subroutine operations common between two or more instructions....
6367000 Fast conversion of encoded tag bits  
The present invention is a method and apparatus for converting a first tag word into a second tag word which correspond to a set of registers. Adjacent bits in the first tag word are determined...
6353863 Terminal  
A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a...
6347294 Upgradeable highly integrated embedded CPU system  
A system and method in accordance with the present invention provides for an embedded CPU system which is upgradeable through the use of an external CPU which can be utilized therewith. In a first...
6347344 Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor  
An integrated multimedia system has a multimedia processor disposed in an integrated circuit. The system comprises a first host processor system which is coupled to the multimedia processor. A...
6339807 Multiprocessor system and the bus arbitrating method of the same  
An arbitrator provided to a processor element requests the utilization of a bus sends a bus request signal and a bus request value according to a priority level of the processor element to the bus,...
6336179 Dynamic scheduling mechanism for an asynchronous/isochronous integrated circuit interconnect bus  
A first counter sequentially counts a plurality of numbers from respective sources requesting transfer of data. Each of the numbers represents an amount of isochronous data to transfer over the bus...
6333928 Integrated multimedia telecommunications server  
The present invention has for its object a telecommunication server for enterprises or like structures. Server characterized in that it is principally constituted, on the one hand, by a central...
6334194 Fault tolerant computer employing double-redundant structure  
A fault tolerant computer comprising plural operation controllers is provided, which can judge and separate a damaged element by using a double-redundant structure without using a triple or...
6321380 Method and apparatus for modifying instruction operations in a processor  
A "soft-patch" allows an instruction or group of instructions to be replaced with a pre-loaded instruction or group of instructions. When an Instruction Fetch Unit (IFU) fetches an instruction, the...
6317820 Dual-mode VLIW architecture providing a software-controlled varying mix of instruction-level and task-level parallelism  
This invention is a very long instruction word data processor including plural data registers, plural functional units and plural program counters and is selectively operable in either a first or...
6314508 RISC type microprocessor and information processing apparatus  
A general purpose register stores a 16-bit fixed length instruction. A bypass circuit speedily outputs the result of a comparison instruction when the next conditional branch instruction is...
6311262 Apparatus for the hierarchical and distributed control of programmable modules in large-scale integrated systems  
The apparatus has a multiplicity of control modules which are assigned to a multiplicity of processing modules for driving purposes. These separate control modules are driven by a superordinate...
6298410 Apparatus and method for initiating hardware priority management by software controlled register access  
An apparatus and method for controlling interrupts in a computer are disclosed, in which programmable software operates to control when data concerning the interrupt having highest priority is to...
6298431 Banked shadowed register file  
An apparatus and method for improving processor performance during multithreaded processing based on the use of a banked shadowed register file for minimizing thread switch overhead.
6298432 One-chip microcomputer including RISC processor and one or more coprocessors having control registers mapped as internal registers for the RISC processor  
A one-chip microcomputer including a Reduced Instruction Set Computer (RISC) type processor and one or more coprocessors for performing processes independent from said RISC type processor. The RISC...
6295598 Split directory-based cache coherency technique for a multi-processor computer system  
A split directory-based cache coherency technique utilizes a secondary directory in memory to implement a bit mask used to indicate when more than one processor cache in a multi-processor computer...
6295599 System and method for providing a wide operand architecture  
The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either...
6289435 Re-use of special purposed registers as general purpose registers  
A method and system for re-using special purpose registers as general purpose registers utilized a special variable type to indicate that a variable may safely be stored in a special purpose...
6289434 Apparatus and method of implementing systems on silicon using dynamic-adaptive run-time reconfigurable circuits for processing multiple, independent data and control streams of varying rates  
An apparatus and method processes data in series or in parallel. Each of the processors operating may perform arithmetic-type functions, logic functions and bit manipulation functions. The...
6279063 Microcomputer system with at least first and second microcomputers each operable in master and slave modes with configurable bus access control terminals and bus use priority controller  
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
6272620 Central processing unit having instruction queue of 32-bit length fetching two instructions of 16-bit fixed length in one instruction fetch operation  
A microcomputer MCU adopting the general purpose register method is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the...
6272067 SRAM synchronized with an optimized clock signal based on a delay and an external clock  
A synchronous SRAM chip that can increase the number of times it may be accessed within a single clock cycle. By knowing the processor's clock speed and determining a critical time, a signal...
6266762 Information processing apparatus  
A general-use register set includes a plurality of registers in a central processing unit body. A register-bank memory has memory regions relevant to the plurality of registers and is connected to...
6263420 Digital signal processor particularly suited for decoding digital audio  
A digital signal processor particularly adapted for decoding digital audio. The barrel shifter of the processor includes logical circuitry, so that operations involving a combination of a logical...
6260087 Embedded configurable logic ASIC  
An Application Specific Integrated Circuit ("ASIC") (10, 30 and 40), which includes at least one hardware, non-programmable functional block (12, 14, 16, 18, 22, 32, 44, 46 and 48), also includes a...
6253305 Microprocessor for supporting reduction of program codes in size  
A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an...
6247121 Multithreading processor with thread predictor  
In one embodiment, a processor includes thread management logic including a thread predictor having state machines to indicate whether thread creation opportunities should be taken or not taken....
H001970 Variable function programmed system  
A variable function calculator utilizes a fixed program memory array such as a programmed read only memory in which a number of programs are stored depending upon the desired functions of the...
6243800 Computer  
The invention relates to computer science, in particular, to a computer system comprising a processor, an input-output switch, an instruction loading switch, instruction memory, and a data access...
6237078 Code segment default operation determination  
A method for determining the default operating mode of a code segment by determining whether an instruction modifies bits in both the upper-order and lower-order halves of a register. A register is...
6233643 Apparatus including a host processor and communications adapters interconnected with a bus  
A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the...
6230255 Communications processor for voice band telecommunications  
The communications processor of the present invention comprises, in a single integrated circuit chip, the combination of a central processing unit (CPU) having an execution unit with an arithmetic...
6230223 Dual purpose apparatus method and system for accelerated graphics or second memory interface  
A multiple use core logic chipset is provided in a computer system that may be configured either as a bridge between an accelerated graphics port ("AGP") bus and host and memory buses, or as a...
6223275 Microprocessor with reduced instruction set limiting the address space to upper 2 Mbytes and executing a long type register branch instruction in three intermediate instructions  
A 32-bit RISC processor is disclosed. The bit length of the instruction set is fixed to 16 bits. SLIL and SLIH instructions that cause the address space of 4 Gbytes to be limited to upper 2 Mbytes...
6212620 Single-chip microcomputer operable in master and slave modes and having configurable bus control terminals  
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
6205534 Apparatus and method for processing data with a plurality of flag groups  
In a data processing apparatus, a decoding unit decodes instructions. A calculator operates N-bit data in accordance with the decoded results. A flag storage unit stores a plurality of flag groups...
6192460 Method and apparatus for accessing data in a shadow set after a failed data operation  
Disclosed is a method and apparatus for accessing data in a computer system after a failed data operation in which I/O process state information is unknown. The failed data operation may cause data...
6189084 Debugging method and monitoring method for analysis instruments  
A method of debugging and a method of monitoring an analysis instrument are provided. A microcomputer of the analysis instrument is provided with a debugging personal computer connected thereto via...
6185670 System for reducing number of opcodes required in a processor using an instruction format including operation class code and operation selector code fields  
A method and apparatus for reducing the number of opcodes required in a computer architecture using an operation class code and an operation selector code. A processor contains a fetch unit which...
6175914 Processor including a combined parallel debug and trace port and a serial port  
A processor provides trace capability. Trace information can be provided over a communication port that is operable both as a trace port and as a parallel debug port. The trace port provides trace...
6175913 Data processing unit with debug capabilities using a memory protection unit  
A data processing unit is described which comprises a central processing unit, a bus coupled with the central processing unit to access a device via address and data lines coupled with the bus. A...
6173408 Processor  
An operation controller, an operation unit and a memory are provided. The operation controller always receives a non-gated clock signal from a clock controller. When an operation initiating signal...
6169929 Automatic polling for user interrupts in a programmable controller using relay ladder logic  
A programmable controller includes memory for storing a ladder logic control program having a plurality of ladder logic instruction rungs. Each rung begins with a start of rung (SOR) instruction. A...
6170048 PC circuits, systems and methods  
An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals...
Matches 151 - 200 out of 387 < 1 2 3 4 5 6 7 8 >