|
Match
|
Document |
Document Title |
|
|
7206894 |
Microcomputer application system, microcomputer, signal processing system and signal processing LSI
An external ROM stores a control program PG for controlling a microcomputer. An MPU executes copy processing to copy a high-speed processing part PGM 1 stored in the external ROM to a high-speed...
|
|
|
7197577 |
Autonomic input/output scheduler selector
The automatic selection of an input/output scheduler in a computing system with a plurality of input/output schedulers is disclosed. Each of the plurality of input/output schedulers is mapped...
|
|
|
7197626 |
Plural microcontrollers for managing CPU allocation and device resources including establishing connections without a centralized operating system
A hardware/firmware layer comprising a Device Manager, an Information Manager, a Memory Manager, and a Process Manager contained in one or more semiconductor chips is disclosed. The...
|
|
|
7194601 |
Low-power decode circuitry and method for a processor having multiple decoders
A processor includes first decoder logic capable of decoding a plurality of encoded instructions comprising a first instruction set, the first decoder logic having an input to receive an encoded...
|
|
|
7185128 |
System and method for machine specific register addressing in external devices
There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports...
|
|
|
7167976 |
Interface for integrating reconfigurable processors into a general purpose computing system
The present invention describes a method and system for an interface for integrating reconfigurable processors into a general purpose computing system. In particular, the system resides in a...
|
|
|
7165006 |
Scan chain disable function for power saving
An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan...
|
|
|
7165128 |
Multifunctional I/O organizer unit for multiprocessor multimedia chips
An apparatus and method for providing enhanced performance for multi-processor multimedia chips. In one embodiment, the present invention is comprised of a data and communication apparatus coupled...
|
|
|
7159211 |
Method for executing a sequential program in parallel with automatic fault tolerance
The present invention provides system and methods for executing a sequential in parallel. Parallel procedures, specified in the program, are executed as parallel slave processes. A process when...
|
|
|
7155718 |
Method and apparatus to suspend and resume on next instruction for a microcontroller
In a computer system including at least one microcontroller, by suspending tasks after execution of particular instructions, such as a load-register-from-external-memory instruction, or when a...
|
|
|
7155600 |
Method and logical apparatus for switching between single-threaded and multi-threaded execution states in a simultaneous multi-threaded (SMT) processor
A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching...
|
|
|
7146488 |
System and method for expanding processor functionality
A system comprises at least one processor, and supporting firmware for supporting at least one function of the at least one processor. The system further comprises logic operable to expand the...
|
|
|
7120903 |
Data processing apparatus and method for generating the data of an object program for a parallel operation apparatus
An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of...
|
|
|
7110830 |
Microprocessor system and method for protecting the system from the exchange of modules
A microprocessor system includes a plurality of modules, among them a microprocessor and at least one storage module for storing the code and/or data for the microprocessor. Stored, in a...
|
|
|
7107361 |
Coupled computers and a method of coupling computers
The present invention provides coupled-type computers wherein a computer can be coupled with computers of the same structure easily, and can be coupled with other computers of the same structure in...
|
|
|
7106600 |
Interposer device
The present invention provides devices and techniques for replacing at least one processor in a multi-processor computer system with an interposer device that maintains at least some of the...
|
|
|
7035906 |
Global network computers
This invention generally relates to one or more computer networks having computers like personal computers or network servers with microprocessors linked by broadband transmission means and having...
|
|
|
7028162 |
Configurable processing block capable of interacting with external hardware
The configurable hardware block is designed to read data stored in a memory according to its configuration, to process the read-out data arithmetically and/or logically and to write the data...
|
|
|
7024538 |
Processor multiple function units executing cycle specifying variable length instruction block and using common target block address updated pointers
A multiprocessor data processing system for executing a program having branch instructions therein, each branch instruction specifying a target address in the program defining an instruction that...
|
|
|
7020854 |
Automated processor generation system for designing a configurable processor and method for the same
An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set,...
|
|
|
7016983 |
System and method for controlling a communication bus
A method for controlling communication. The method sends a first instruction from a first processor to a first device via a processor bus in electrical communication with a first bus, sends a...
|
|
|
7000092 |
Heterogeneous multi-processor reference design
The present invention is directed to a system and method for heterogeneous multiprocessor reference design. In an aspect of the present invention, a method of designing a multiprocessor integrated...
|
|
|
6993597 |
Terminal apparatus
A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a...
|
|
|
6981074 |
Descriptor-based load balancing
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently...
|
|
|
RE38911 |
Modular digital image processing via an image processing chain with modifiable parameter controls
Aspects for allowing variably controlled alteration of image processing of digital image data in a digital image capture device include forming an image processing chain with two or more image...
|
|
|
6963829 |
Method and apparatus for interfacing a spectrum digital incorporated TMS470 evaluation board with a spectrum digital incorporated TMS320LC54X evaluation board
A bridge board connects a TMS470 processor evaluation module and a TMS320C54XX processor evaluation module. The bridge board performs translation of signal formats on both of the boards and also...
|
|
|
6959365 |
Microcomputer including a flash memory and a flash memory rewrite program stored therein
A microcomputer with a built-in flash memory is obtained in which the flash memory can be properly rewritten with a rewrite program kept placed on the flash memory and without requiring additional...
|
|
|
6954841 |
Viterbi decoding for SIMD vector processors with indirect vector element access
A configuration of vector units, digital circuitry and associated instructions is disclosed for the parallel processing of multiple Viterbi decoder butterflies on a programmable digital signal...
|
|
|
6948005 |
Peripheral device for programmable controller
A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying...
|
|
|
6938118 |
Controlling access to a primary memory
The invention relates to a primary memory such as a dynamic random access memory, and a method and controller for controlling access to such a memory. The access control for the primary memory ( 60...
|
|
|
6931513 |
Data converter with statistical domain output
An integrated circuit having statistical processing capability. The integrated circuit has an input for receiving input data in a first data domain. A data converter is provided for converting...
|
|
|
6928535 |
Data input/output configuration for transfer among processing elements of different processors
An image input section and a signal processing section are provided. The image input section includes an array of pixel in which a plurality of pixels having a CMOS type photoelectric converting...
|
|
|
6925554 |
Method of programming USB microcontrollers
An apparatus comprising a microcontroller configured to (i) send or receive data over one or more data lines when in a first mode and (ii) be programmed through said data lines when in a second mode.
|
|
|
6920545 |
Reconfigurable processor with alternately interconnected arithmetic and memory nodes of crossbar switched cluster
A reconfigurable processor architecture. A reconfigurable processor is an array of a multiplicity of various functional elements, between which the interconnections may be programmably configured....
|
|
|
6917220 |
Semiconductor device and a method for checking state transition thereof
A semiconductor device includes a state code register that stores a state code representing a present internal state. A state transition logic unit is configured to determine a state code for a...
|
|
|
6907560 |
Forward error correction (FEC) on a link between ICs
An apparatus suitable for generating a signal for transmission over a link between two ICs is provided. The apparatus receives an input signal comprising payload data to be transmitted and...
|
|
|
6889271 |
Methods and apparatus for meter I/O board addressing and communication
The present invention, in one embodiment, is a method for input/output (I/O) board addressing and communications in an electronic electric meter having a microcomputer. The method includes steps of...
|
|
|
6885376 |
System, method, and computer program product for near-real time load balancing across multiple rendering pipelines
A system, method, and computer program product for creating a sequence of computer graphics frames, using a plurality of rendering pipelines. For each frame, each rendering pipeline receives a...
|
|
|
6882940 |
Methods and devices for prediction of hypoglycemic events
Described herein are methods, devices, and microprocessors useful for predicting a hypoglycemic event in a subject. The hypoglycemic predictive approach described herein utilizes information...
|
|
|
6880033 |
Methods for configuring separate accessibility of each channel of a dual channel SCSI chip
A method for configuring channels of a dual channel SCSI chip is provided which includes setting at least one bit in a first configuration space within a first channel control in the dual channel...
|
|
|
6862634 |
Mechanism to improve performance in a multi-node computer system
In a distributed multi-node computer system each switch provides routing of data packets between CPU nodes, I/O nodes, and memory nodes. Each switch is connected through a corresponding I/O node to...
|
|
|
6850879 |
Microcomputer with emulator interface
A microcomputer includes a processor and an emulator interface circuit that provides processor state information to an external emulator. The emulator interface circuit operates at a clock speed...
|
|
|
6851042 |
Audio, fax and modem capabilities with a digital signal processor of a sound card of a computer system
An optional card including a digital signal processor (DSP) for use by a modem daughter board, where the modem daughter board is equipped with a data access arrangement (DAA) for upgrading a...
|
|
|
6845229 |
Educational instruction system
A main server 5 registers information about lecturers and students, and it introduces the lecturers to the students automatically. Thus, the system assists the lecture of the lecturers to be...
|
|
|
6826628 |
PCI-PCMCIA smart card reader
A method and apparatus is disclosed for implementing an integrated video card and smart card reader. A single processor is used to perform both video and smart card reader functions. The processor...
|
|
|
6820189 |
Computation core executing multiple operation DSP instructions and micro-controller instructions of shorter length without performing switch operation
A computation core for executing programmed instructions includes an execution block for performing digital signal processor operations in response to digital signal processor instructions and for...
|
|
|
6820143 |
On-chip data transfer in multi-processor system
A system and method are provided for improving performance of a computer system by providing a direct data transfer between different processors. The system includes a first and second processor....
|
|
|
6802017 |
Partial enabling of functional unit based on data and size pair in register
An SZ (size information) section is provided for each of registers that make up a register file. Suppose an instruction decoded requests that operand data of a particular size be loaded from a RAM...
|
|
|
6789183 |
Apparatus and method for activation of a digital signal processor in an idle mode for interprocessor transfer of signal groups in a digital signal processing unit
In a digital processing unit having a plurality of digital signal processors, a first digital signal processor can request a direct transfer of a signal group stored in the memory unit of a second...
|
|
|
6785743 |
Template data transfer coprocessor
The template data transfer coprocessor (TDTP) offloads block data transfer operations from a mediaprocessor. A uni-block template, program-guided template, an indirect template and queue-based...
|