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7620780 Multiprocessor system with cache controlled scatter-gather operations  
Dynamic cache architecture for a multi-processor array. The system includes a plurality of processors, with at least one of the processors configured as a parent processor, and at least one of the...
7606867 Ordered application message delivery using multiple processors in a network element  
A data processing apparatus comprises a plurality of processors and message processing logic operable for establishing one of the processors as a master processor and all other processors as slave...
7587717 Dynamic master/slave configuration for multiple expansion modules  
A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes...
7574582 Processor array including delay elements associated with primary bus nodes  
There is disclosed a processor array, which achieves an approximately constant latency. Communications to and from the farthest array elements are suitably pipelined for the distance, while...
7525548 Video processing with multiple graphical processing units  
One embodiment of a video processor includes a first media processing device coupled to a first memory and a second media processing device coupled to a second memory. The second media processing...
7502958 System and method for providing firmware recoverable lockstep protection  
According to at least one embodiment, a method comprises detecting loss of lockstep for a pair of processors. The method further comprises triggering, by firmware, an operating system to idle the...
7487221 Network system, distributed processing method and information processing apparatus  
A network system by which the processing speed of the entire system can be enhanced. The network system includes a number of information processing apparatus connected to each other through a...
7457939 Processing system with dedicated local memories and busy identification  
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and...
7454547 Data exchange between a runtime environment and a computer firmware in a multi-processor computing system  
A method, system, apparatus, and computer-readable medium for exchanging data between an application program and a firmware in a computer system having multiple CPUs are provided. According to the...
7424595 System for managing circuitry of variable function information processing circuit and method for managing circuitry of variable function information processing circuit  
Configuration management information having circuit configuration information for altering a circuit configuration of an FPGA ( 12 ) is stored in a memory ( 13 ), the configuration management...
7395410 Processor system with an improved instruction decode control unit that controls data transfer between processor and coprocessor  
A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an...
7380037 Data transmitter between external device and working memory  
A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU...
7356733 System and method for system firmware causing an operating system to idle a processor  
According to one embodiment, a method comprises system firmware instructing a system's operating system to idle a processor, and responsive to the instructing, the operating system idling the...
7346051 Slave device, master device and stacked device  
A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of...
7237041 Systems and methods for automatic assignment of identification codes to devices  
A system and method for automatically and uniquely assigning identification codes to a plurality of slave processors. A master processor having communication port is linked to a first slave...
7234011 Advanced microcontroller bus architecture (AMBA) system with reduced power consumption and method of driving AMBA system  
In an advanced microcontroller bus architecture (AMBA) system with reduced power consumption, a signal transition is allowed to occur only in loads required for transferring bus signals by...
7159211 Method for executing a sequential program in parallel with automatic fault tolerance  
The present invention provides system and methods for executing a sequential in parallel. Parallel procedures, specified in the program, are executed as parallel slave processes. A process when...
7152125 Dynamic master/slave configuration for multiple expansion modules  
A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes...
7137121 Data-processing circuit and method for switching between application programs without an operating system  
A data-processing circuit includes first and second cooperating processors where one of the processors context switches between applications without running an operating system. In one...
7127594 Multiprocessor system and program optimizing method  
A multiprocessor system capable of responding to various types of processing to improve the processing efficiency of the entire system. Each of a plurality of processors holds information...
7076676 Sequence alignment logic for generating output representing the slowest from group write slaves response inputs  
A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID...
7072803 Device and process for acquisition of measurements using a digital communication bus, particularly used during aircraft tests  
The invention relates to a device for acquisition of measurements using a digital communication bus ( 10 ) and a computer system. The device includes a bus arbitrator, several items of slave...
7035906 Global network computers  
This invention generally relates to one or more computer networks having computers like personal computers or network servers with microprocessors linked by broadband transmission means and having...
6952713 Information processing device  
The invention relates to an information processing device ( 1 ), including a user control unit ( 2 ) for the selection of units of primary information to be processed and functions to be invoked....
6952618 Input/output control systems and methods having a plurality of master and slave controllers  
Apparatus and methods for controlling a system that operates responsive to a plurality of input control signals are disclosed. During operation the system generates a plurality of output...
6922736 Computer system and data processing method  
A computer system has a node and a service processor (SVP) connected together via a diagnosis section. An input/output (I/O) unit is connected to the SVP. The diagnosis section has a serial...
6907454 Data processing system with master and slave processors  
A data processing system comprises a master processor ( 10 ), a slave processor ( 30 ), a memory ( 50 ), and a bus subsystem ( 20 ) interconnecting the master processor ( 10 ), the slave processor...
6839866 System and method for the use of reset logic in high availability systems  
A method of providing reset logic in high availability computer systems is disclosed. The illustrative embodiment of the present invention uses probability theory in combination with redundant...
6836840 Slaves with identification and selection stages for group write  
A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID...
6831648 Synchronized image display and buffer swapping in a multiple display environment  
A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the...
6826673 Communications protocol processing by real time processor off-loading operations to queue for processing by non-real time processor  
A communication protocol processing unit by a multiprocessor is disclosed, and includes a first processor for performing a process demanding a real time property on a stream of communication data;...
6809733 Swap buffer synchronization in a distributed rendering system  
A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the...
6789182 System and method for logging computer event data and physical components of a complex distributed system  
A system for collecting events relating to multiple distributed physical systems includes multiple event collection cards ( 100 ), each receiving events from one of the distributed physical...
6782468 Shared memory type vector processing system, including a bus for transferring a vector processing instruction, and control method thereof  
A shared memory type vector processing system in which CPUs are connected by a bus for transferring a vector processing instruction generated from any of the CPUs to each of the CPUs, and the...
6754811 Operating system device centric agent  
A USB device centric agent is associated with an operating system. The agent software is only required to be loaded once and then it will function with multiple compatible USB devices. A standard...
6735683 Single-chip microcomputer with hierarchical internal bus structure having data and address signal lines coupling CPU with other processing elements  
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
6668288 Telecommunications data conferencing platform having secure firewall wherein access is restricted to messages originating from server but conference data pass freely  
A telecommunications data conferencing platform has a secure zone and a partly secure zone connected by a secure firewall. The secure zone contains a master data server, a billing system a...
6604189 Master/slave processor memory inter accessability in an integrated embedded system  
An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or...
6597956 Method and apparatus for controlling an extensible computing system  
A Virtual Server Farm (VSF) is created out of a wide scale computing fabric (“Computing Grid”) which is physically constructed once and then logically divided up into VSFs for various...
6591294 Processing system with microcomputers each operable in master and slave modes using configurable bus access control terminals and bus use priority signals  
A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an...
6574725 Method and mechanism for speculatively executing threads of instructions  
A processor architecture containing multiple closely coupled processors in a form of symmetric multiprocessing system is provided. The special coupling mechanism allows it to speculatively execute...
6564179 DSP emulating a microcontroller  
The present invention provides a processor device and technique having the capability of providing a two-processor solution with only one processor. In accordance with the principles of the present...
6560750 Method for providing master-slave heat-swapping apparatus and mechanism on a mono-ATA bus  
The present invention relates to a method for providing a master-slave hot-swapping apparatus and mechanism for use with an ATA bus. A bus controller and a bus separator are employed for isolating...
6553465 Multiprocessor system with distributed shared memory having hot plug function for main memories  
A multiprocessor system of a distributed shared memory structure has a hot plug function for main memories. Each of nodes of the multiprocessor system has a processor, an IO unit, a main memory, a...
6526583 Interactive set-top box having a unified memory architecture  
According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device,...
6496517 Direct attach of interrupt controller to processor module  
A system, such as an AMBA based system, wherein an interrupt controller is coupled directly to a processor, thereby providing that the processor can access the interrupt controller without having...
6487617 Source-destination re-timed cooperative communication bus  
A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when the addressed storage location in the data...
6467009 Configurable processor system unit  
The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.
6460129 Pipeline operation method and pipeline operation device to interlock the translation of instructions based on the operation of a non-pipeline operation unit  
A pipeline operation method and a pipeline operation device in which an operation result of an operation unit can be effectively written to a register. In the pipeline operation method and the...
6446192 Remote monitoring and control of equipment over computer networks using a single web interfacing chip  
A single integrated circuit chip interfaces device control circuitry of a device to a client machine via a computer network. The chip comprises an internal data bus; a central processing unit...
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