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8171188 |
Method of handling successive bitstream extraction and packing and related device
To handle boundary conditions efficiently during bitstream extraction, a predetermined number of bits are extracted from the bitstream register starting from a most significant bit of the bitstream...
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8151053 |
Hierarchical storage control apparatus, hierarchical storage control system, hierarchical storage control method, and program for controlling storage apparatus having hierarchical structure
An extractor extracts a plurality of storage areas storing identical data strings therein from the storage areas of a lower storage layer. A layer storage controller associates the extracted...
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8145723 |
Complex remote update programming idiom accelerator
A remote update programming idiom accelerator is configured to detect a complex remote update programming idiom in an instruction sequence of a thread. The complex remote update programming idiom...
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8117351 |
Serial parallel interface for data word architecture
Subject matter disclosed herein relates to techniques involving transitioning serial data into a serial parallel interface.
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8095776 |
Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
A semiconductor device correctly switches endian modes regardless of the current endian mode of an interface. The semiconductor device includes a switching circuit and a first register. The...
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8082315 |
Programming idiom accelerator for remote update
A remote update programming idiom accelerator identifies a remote update programming idiom in an instruction sequence of a thread running on a processing unit of a data processing system. The...
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8082372 |
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
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8069195 |
Method and system for a wiring-efficient permute unit
A method of providing wiring efficiency in a permute unit. Multiple selectors receive input data and shared control signals from multiple register files. The permute unit includes multiple...
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7995750 |
Privacy-preserving concatenation of strings
A system for contributing to a concatenation of a first string and a second string may include a communication unit to receive an encrypted representation of a second share of the second string,...
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7991987 |
Comparing text strings
A shorter and a longer text string may be compared. Instead of simply comparing the characters only one character at a time, more than one character can be compared at a time. In addition, a null...
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7986780 |
Privacy-preserving substring creation
A system to contribute to creating a substring of a string may include a communication unit and a processing unit. The communication unit may be configured to receive an encrypted representation of...
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7975080 |
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
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7966482 |
Interleaving saturated lower half of data elements from two source registers of packed data
An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to pack the packed data...
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7953955 |
Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture
A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a...
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7949697 |
Bit field operation circuit
A bit field operation circuit has a first shift unit, a mask shift amount control circuit, a second shift unit, a logic operation unit, and a selection unit. The first shift unit outputs a first...
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7934077 |
Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The...
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7908463 |
Immediate and displacement extraction and decode mechanism
An extraction and decode mechanism for acquiring and processing instructions and the corresponding constant(s) embedded within the instructions. The extraction and decode mechanism may be included...
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7904699 |
Processing unit incorporating instruction-based persistent vector multiplexer control
Persistent vector multiplexer control is used in a vector-based execution unit to control the shuffling of words in operand vectors processed by the execution unit. In addition, a persistent...
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7904700 |
Processing unit incorporating special purpose register for use with instruction-based persistent vector multiplexer control
A software-accessible special purpose register is architected into a processing unit in order to implement persistent vector multiplexer control of a vector-based execution unit. A persistent...
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7899904 |
Hardware processing of regular expressions
A system and method for hardware processing of regular expressions is disclosed. A register bank is loaded with state information associated with one or more states of a state machine. State...
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7895423 |
Method for extracting fields from packets having fields spread over more than one register
Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register...
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7873066 |
Streaming direct inter-thread communication buffer packets that support hardware controlled arbitrary vector operand alignment in a densely threaded network on a chip
A computer-implemented method, system and computer program product for arbitrarily aligning vector operands, which are transmitted in inter-thread communication buffer packets within a highly...
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7870159 |
Algorithm for sorting bit sequences in linear complexity
A computer program product and associated algorithm for sorting S sequences of binary bits. The S sequences may be integers, floating point numbers, or character strings. The algorithm is executed...
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7870361 |
Aligning IP payloads on memory boundaries for improved performance at a switch
A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Internet...
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7853860 |
Programmable signal and processing circuit and method of depuncturing
A programmable signal processing circuit has an instruction processing circuit (23, 24, 26), with an instruction set that comprises a depuncture instruction. The instruction processing circuit (23,...
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7840789 |
Data hiding in compiled program binaries for supplementing computer functionality
Bit reductions in program instructions are achieved by determining the set of bit patterns in bit locations of the instructions. If only a subset of bit patterns is present in the instructions,...
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7822955 |
Data processing apparatus and method for utilizing endianess independent data values
The present invention provides a technique for swapping data values within a data word. In particular, a single endian reverse instruction is provided to cause independent swap operations to be...
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7814303 |
Execution of a sequence of vector instructions preceded by a swizzle sequence instruction specifying data element shuffle orders respectively
Operand vector multiplexer sequence control is used in a vector-based execution unit to control the shuffling of data elements in operand vectors used by a sequence of vector instructions processed...
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7813429 |
System and method for segmentation of macroblocks
A method for processing a video stream is disclosed. The method generally includes the steps of (A) checking a respective first motion vector for each of a plurality of blocks in a group within an...
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7787537 |
Method and apparatus for low-memory high-performance discrete cosine transform coefficient prediction
A method and an apparatus for discrete cosine transform coefficient prediction are disclosed. The method comprises the steps as follows: providing a discrete cosine transformed block; performing an...
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7773005 |
Method and apparatus for decoding variable length data
System and method for decompressing data. A compressed data stream including contiguous variable length data blocks is received, each variable length data block including multiple contiguous...
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7769753 |
Method and system for retrieving a data pattern
A data retrieval system includes a retrieval request block for generating a retrieval key including a current state number and a current character string including N characters latched from an...
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7765338 |
Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller
Techniques for providing improved data distribution to and collection from multiple memories are described. Such memories are often associated with and local to processing elements (PEs) within an...
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7743231 |
Fast sparse list walker
Provided are a method, information processing system, and computer readable medium for identifying active bits in a vector. The method comprises receiving a pointer associated with a vector of...
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7734853 |
Latency dependent data bus transmission
In a system where data is transmitted from a source device to a destination device via one or more buses, transmission mode selecting circuitry is provided to select one of a first transmission...
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7730292 |
Parallel subword instructions for directing results to selected subword locations of data processor result register
In the context of a microprocessor and a program, the invention provides parallel subword compare instructions that store results in a selectable intra-register subword location. In a targeting...
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7725699 |
Data byte insertion circuitry
A data byte insertion circuit includes circuitry to generate derivative intermediate data words from input data words of a current and a preceding cycle, repositioning data bytes of the input data...
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7721077 |
Performing endian conversion
A computing system may support an endian toggle register (ETR) and the endianess of the endian toggle register may be designated using a set endian bit (SEB) or a clear endian bit (CEB)...
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7707547 |
System and method for creating target byte code
A system and method for converting byte code of a first type into byte code of a second type. Byte code of a first type is received as input. The first byte code is converted into constituent byte...
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7698542 |
Circuit and method for comparing program counter values
A circuit and a method of examining in a microprocessor a section of a first range of values and a second range of values each comprising a lower boundary value and an upper boundary value is...
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7685408 |
Methods and apparatus for extracting bits of a source register based on a mask and right justifying the bits into a target register
Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in...
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7685407 |
Semiconductor device and data processing system selectively operating as one of a big endian or little endian system
The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The...
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7600104 |
Method and system for parallel vector data processing of vector data having a number of data elements including a defined first bit-length
System and method are provided for parallel vector data processing having a data processor capable of vector data having a defined first bit-length. In one embodiment, at least one of first and...
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7590832 |
Information processing device, compressed program producing method, and information processing system
An information processing device for executing a compressed program includes: an instruction buffer; a first selector for selectively outputting one of a set of signals obtained by dividing the...
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7587535 |
Data transfer control device including endian conversion circuit with data realignment
When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the...
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7587526 |
Endianness independent data structures
Embedding endianness information within data and sending and receiving data with the embedded endianness information. Data may be contained in a data structure. To embed endianness information in a...
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7581091 |
System and method for extracting fields from packets having fields spread over more than one register
Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register...
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7565516 |
Word reordering upon bus size resizing to reduce Hamming distance
In a system having a first device 10 and a second device 8 between which data values are transferred via an N-bit bus, a resizing unit 18 and an M-bit bus, reordering of the data is performed such...
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7529918 |
System and method for efficiently performing bit-field extraction and bit-field combination operations in a processor
A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a...
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7523261 |
Method and circuit arrangement for adapting a program to suit a buffer store
A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a...
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