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7603346 |
Integrated search engine devices having pipelined search and b-tree maintenance sub-engines therein
A pipelined search engine device, such as a longest prefix match (LPM) search engine device, includes a hierarchical memory and a pipelined tree maintenance engine therein. The hierarchical memory...
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7600104 |
Method and system for parallel vector data processing of vector data having a number of data elements including a defined first bit-length
System and method are provided for parallel vector data processing having a data processor capable of vector data having a defined first bit-length. In one embodiment, at least one of first and...
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7590832 |
Information processing device, compressed program producing method, and information processing system
An information processing device for executing a compressed program includes: an instruction buffer; a first selector for selectively outputting one of a set of signals obtained by dividing the...
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7587535 |
Data transfer control device including endian conversion circuit with data realignment
When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the...
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7587526 |
Endianness independent data structures
Embedding endianness information within data and sending and receiving data with the embedded endianness information. Data may be contained in a data structure. To embed endianness information in a...
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7581091 |
System and method for extracting fields from packets having fields spread over more than one register
Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register...
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7565516 |
Word reordering upon bus size resizing to reduce Hamming distance
In a system having a first device 10 and a second device 8 between which data values are transferred via an N-bit bus, a resizing unit 18 and an M-bit bus, reordering of the data is performed...
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7529918 |
System and method for efficiently performing bit-field extraction and bit-field combination operations in a processor
A system and method for efficiently performing bit-field extraction and bit-field combination operations in a processor is provided. The system includes a plurality of general purpose registers, a...
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7523261 |
Method and circuit arrangement for adapting a program to suit a buffer store
A method for changing a succession of instruction words including providing a set of machine words, each machine word being associated with an address from a set of addresses, providing a...
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7500089 |
SIMD processor with exchange sort instruction operating or plural data elements simultaneously
An SIMD type microprocessor having a plurality of processor elements, wherein data stored in a specific register included in each processor element and data stored in an operand-designated source...
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7493481 |
Direct hardware processing of internal data structure fields
In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code...
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7480783 |
Systems for loading unaligned words and methods of operating the same
Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a...
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7467138 |
Algorithm for sorting bit sequences in linear complexity
A method and associated algorithm for in-place sorting S sequences of binary bits stored contiguously in an array within a memory device of a computer system prior to the sorting. Each sequence...
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7464255 |
Using a shuffle unit to implement shift operations in a processor
A method and mechanism for performing shift operations using a shuffle unit. A processor includes a shuffle unit configured to perform shuffle operations responsive to shuffle instructions. The...
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7464254 |
Programmable processor apparatus integrating dedicated search registers and dedicated state machine registers with associated execution hardware to support rapid application of rulesets to data
A rule processor and method for using the same are disclosed. In one embodiment, the rule processor comprises a general purpose register file, an instruction sequencer to provide instructions, a...
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7444488 |
Method and programmable unit for bit field shifting
A method and a programmable unit for bit field shifting in a memory device in a programmable unit as a result of the execution of an instruction, in which a bit segment is shifted within a first...
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7441104 |
Parallel subword instructions with distributed results
The present invention provides for parallel subword instructions that cause results to be non-contiguously stored in a result register. For example, a targeting-type instruction can specify...
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7434040 |
Copying of unaligned data in a pipelined operation
Methods, computer readable media and computing devices including program instructions are provided for copying unaligned data. One method embodiment includes using 12 execution units to move 16...
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7403835 |
Device and method for programming an industrial robot
In a device and method for programming an industrial robot using a simulation program, control commands are issued by a handheld programming device and these commands are visualized on an image...
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7389408 |
Microarchitecture for compact storage of embedded constants
An instruction stream having variable length instructions with embedded constants (e.g. immediate values and displacements) is translated into a stream of operations and a corresponding stream of...
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7370184 |
Shifter for alignment with bit formatter gating bits from shifted operand, shifted carry operand and most significant bit
An apparatus for shifting data is disclosed. The apparatus includes a shifter, a register, and a shift post processor. The shifter shifts an operand according to an offset parameter, thereby...
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7363478 |
Retrieving multi-byte vector elements from byte indexed table using replicated and consecutive number added indices for each element index
A lookup operation is carried out on a data table by logically dividing the data table into a number of smaller sets of data that can be indexed with a single byte of data. Each set of data...
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7356676 |
Extracting aligned data from two source registers without shifting by executing coprocessor instruction with mode bit for deriving offset from immediate or register
A processor-based system may include a main processor and a coprocessor. The coprocessor handles instructions that include opcodes specifying a data processing operation to be performed by the...
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7353371 |
Circuit to extract nonadjacent bits from data packets
A method and device to copy data fields from one or more source packets to one or more result packets. In a SET function, adjacent data fields in a source packet is copied to respective destination...
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7350058 |
Shift and insert instruction for overwriting a subset of data within a register with a shifted result of another register
A data processing system 2 is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that...
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7346430 |
Image transmission device and method, transmitting device and method, receiving device and method, and robot apparatus
An image transmission device and method, a transmitting device and method, a receiving device and method, and robot apparatus are capable of effectively transmitting the image data of multiple...
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7340588 |
Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code
This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code...
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7334116 |
Bit manipulation on data in a bitstream that is stored in a memory having an address boundary length
A bit manipulation processor, system and method are provided which reduces the number of operations performed during data processing. An additional register is used as a buffer. The buffer has a...
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7315937 |
Microprocessor instructions for efficient bit stream extractions
A method of extracting bits of a bit stream including retrieving bits from the bit stream into an accumulator, specifying a size value specifying a number of bits to extract, storing a position...
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7315261 |
Method for converting data from pixel format to bitplane format
This invention efficiently converts normal pixel data into bit plane data. A sequence of pack, bitwise shuffle, masking, rotate and merging operations transform tile from pixel form to bit plane...
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7313660 |
Data stream frequency reduction and/or phase shift
A frequency reduction or phase shifting circuit has an input receiving an input data stream having an input frequency and a representation of desired output frequency. A splitter splits the input...
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7277574 |
Methods and systems for feature selection
Methods and systems for feature selection are described. In particular, methods and systems for feature selection for data classification, retrieval, and segmentation are described. Certain...
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7275147 |
Method and apparatus for data alignment and parsing in SIMD computer architecture
Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a...
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7263563 |
Multi-bus driver apparatus and method for driving a plurality of buses
A bus driving method and apparatus for driving a plurality of buses including a control logic for generating and outputting control signals and bus selection signals, a byte rotator for dividing...
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7260711 |
Single instruction multiple data processing allowing the combination of portions of two data words with a single pack instruction
A data processing system is provided with an instruction (PKH) that combines a packing operation of respective portions of input operand data words (Rn, Rm) into an output data word (Rd) together...
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7257697 |
Processing system with general purpose execution unit and separate independently operating data string manipulation unit
A processing system optimized for data string manipulations includes data string execution circuitry associated with a bus interface unit or memory controller. Cache coherency is maintained, and...
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7254699 |
Aligning load/store data using rotate, mask, zero/sign-extend and or operation
The present invention relates generally to microprocessor or microcontroller architecture, and particularly to an architecture structured to handle unaligned memory references. A method is...
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7251722 |
Semantic processor storage server architecture
A storage server uses a semantic processor to parse and respond to client requests. A direct execution parser in the semantic processor parses an input stream, comprising client storage server...
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7237097 |
Partial bitwise permutations
Partial bitwise permutation instructions are provided in a microprocessor or microcontroller. Partial bitwise permutations may be specified by one or more of the following: a destination specifier,...
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7231505 |
Aligning IP payloads on memory boundaries for improved performance at a switch
A network device includes an alignment module to align payloads of received frames on memory boundaries in a buffer memory. The frames may be Ethernet frames which encapsulate IP (Inernet Protocol)...
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7210134 |
Deterring reverse-engineering of software systems by randomizing the siting of stack-based data
A given software process is composed on one or more threads of execution. Each thread possesses its own stack, a region of memory set aside by the operating system for that thread to store data....
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7210023 |
Data processing apparatus and method for moving data between registers and memory in response to an access instruction having an alignment specifier identifying an alignment to be associated with a start address
The present invention provides a data processing apparatus and method for performing aligned access operations. The data processing apparatus comprises a register data store having a plurality of...
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7188115 |
Processing fixed-format data in a unicode environment
A computer system and object-oriented method and class for use with the computer system to convert data in Unicode format back and forth to data having a fixed-length format, such as EBCDIC, and to...
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7155601 |
Multi-element operand sub-portion shuffle instruction execution
An apparatus and method for performing a shuffle operation on packed data is described. In one embodiment, a 128-bit packed data operand having at eight data elements is accessed. In one...
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7143231 |
Method and apparatus for performing packet classification for policy-based packet routing
A method and apparatus for performing packet classification in a digital signal processor for policy-based packet routing. For one embodiment, the digital signal processor includes a policy...
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7139905 |
Dynamic endian switching
The dynamic switching of a bi-endian processor between endian modes is described. A device having the bi-endian processor may also have an endian select circuit. The endian select circuit may...
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7139904 |
Data byte insertion circuitry
A data byte insertion circuit includes circuitry to generate derivative intermediate data words from input data words of a current and a preceding cycle, repositioning data bytes of the input data...
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7133040 |
System and method for performing an insert-extract instruction
An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is...
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7127595 |
Method and system for configuring to a desired order the order of a data array
A method and system of configuring an array of data is disclosed. The method and system comprise generating an array of data an order and reconfiguring the array of data into a plurality sub arrays...
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7114055 |
Reduced instruction set computer architecture with duplication of bit values from an immediate field of an instruction multiple times in a data word
A reduced instruction set computer architecture implemented on a field programmable gate array includes a parallel bit shifter capable of reversible shifts and bit reversals, a Reed-Muller Boolean...
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