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7600095 Executing scatter operation to parallel computer nodes by repeatedly broadcasting content of send buffer partition corresponding to each node upon bitwise OR operation  
Executing a scatter operation on a parallel computer includes: configuring a send buffer on a logical root, the send buffer having positions, each position corresponding to a ranked node in an...
7594250 Method and system of program transmission optimization using a redundant transmission sequence  
A system and method of optimizing transmission of a program to multiple users over a distribution system, with particular application to video-on-demand for a CATV network. The system includes, at...
7523293 Spawn-join instruction set architecture for providing explicit multithreading  
The invention presents a unique computational paradigm that provides the tools to take advantage of the parallelism inherent in parallel algorithms to the full spectrum from algorithms through...
7506138 Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers  
A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical...
7454595 Distributed processor allocation for launching applications in a massively connected processors complex  
A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the...
7447676 Method and system of collecting execution statistics of query statements  
A method and system of collecting execution statistics of query statements is disclosed. An execution plan is generated for a query statement in one embodiment of the invention. The execution plan...
7437534 Local and global register partitioning technique  
A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each...
7401333 Array of parallel programmable processing engines and deterministic method of operating the same  
The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least...
7362762 Distributed packet processing with ordered locks to maintain requisite packet orderings  
Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets, especially for maintaining requisite...
7356819 Task distribution  
Methods, signals, devices and systems are provided for matching tasks with processing units. A region within a multi-faceted task space is allocated to a processing unit. A point in the...
7281118 Sending thread message generated using DCR command pointed message control block storing message and response memory address in multiprocessor  
A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or...
7162615 Data transfer bus communication using single request to perform command and return data to destination indicated in context to allow thread context switch  
Systems and methods that allow for performing a single transaction that both instructs a device to perform an operation and return the resulting data to a processor without the processor having to...
7103752 Method and apparatus for broadcasting messages with set priority to guarantee knowledge of a state within a data processing system  
A method, apparatus, and computer instructions for broadcasting information. A change in data used by a number of processors in the data processing system is identified. A message is sent to the...
7093104 Processing modules for computer architecture for broadband networks  
A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and...
7000098 Passing a received packet for modifying pipelining processing engines' routine instructions  
In one embodiment, a method is provided. The method of this embodiment includes generating, by a processor that includes a plurality of processing engines capable of executing program instructions,...
6981074 Descriptor-based load balancing  
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently...
6952713 Information processing device  
The invention relates to an information processing device ( 1 ), including a user control unit ( 2 ) for the selection of units of primary information to be processed and functions to be invoked....
6922736 Computer system and data processing method  
A computer system has a node and a service processor (SVP) connected together via a diagnosis section. An input/output (I/O) unit is connected to the SVP. The diagnosis section has a serial...
6892286 Shared memory multiprocessor memory model verification system and method  
A system and method for verifying a memory consistency model for a shared memory multiprocessor computer systems generates random instructions to run on the processors, saves the results of the...
6789182 System and method for logging computer event data and physical components of a complex distributed system  
A system for collecting events relating to multiple distributed physical systems includes multiple event collection cards ( 100 ), each receiving events from one of the distributed physical...
6754892 Instruction packing for an advanced microprocessor  
A process for packing an instruction word including providing a word value representing an instruction word into which an operation is to be fit be equal to some initial value having a plurality of...
6721813 Computer system implementing a system and method for tracking the progress of posted write transactions  
A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem...
6691220 Multiprocessor speculation mechanism via a barrier speculation flag  
A method of operation within a processor that permits load instructions following barrier instructions in an instruction sequence to be issued speculatively. The barrier instruction is executed and...
6671565 Electronic control apparatus having mode check function  
An electronic control apparatus for a control object makes a mode check before each program part is retrieved even at a predetermined start timing, and inhibits a retrieval of program parts...
6651157 Multi-processor system and method of accessing data therein  
A multi-processor system ( 10 ) includes a plurality of processors ( 12 ). Each processor ( 12 ) has an integrated memory ( 16 ) operable to provide, receive, and store data. Each processor ( 12 )...
6609192 System and method for asynchronously overlapping storage barrier operations with old and new storage operations  
Disclosed is a multiprocessor data processing system that executes loads transactions out of order with respect to a barrier operation. The data processing system includes a memory and a plurality...
6606702 Multiprocessor speculation mechanism with imprecise recycling of storage operations  
Disclosed is a method of operating a processor, by which a speculatively issued load request, which fetches incorrect data, is recycled. An instruction sequence, which includes a barrier...
6557048 Computer system implementing a system and method for ordering input/output (IO) memory operations within a coherent portion thereof  
A computer system is presented which implements a system and method for ordering input/output (I/O) memory operations. In one embodiment, the computer system includes a processing subsystem and an...
6553442 Bus master for SMP execution of global operations utilizing a single token with implied release  
In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined...
6473849 Implementing locks in a distributed processing system  
A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of...
6389513 Disk block cache management for a distributed shared memory computer system  
A buffer cache management structure, or metadata, for a computer system such as a NUMA (non-uniform memory access) machine, wherein physical main memory is distributed and shared among separate...
6389526 Circuit and method for selectively stalling interrupt requests initiated by devices coupled to a multiprocessor system  
A circuit and method is provided for selectively stalling interrupt requests originating devices coupled to a multiprocessor system. The multiprocessor system includes a plurality of circuit nodes...
6351798 Address resolution unit and address resolution method for a multiprocessor system  
The present invention provides an address resolution method for use in a multiprocessor system with distributed shared memory. The method allows users to change a memory configuration and a system...
6330583 Computer network of interactive multitasking computers for parallel processing of network subtasks concurrently with local tasks  
A local area computer network provides distributed parallel processing. The network comprises a plurality of workstations or personal computers, each having preemptive multitasking for the...
6304901 Multiple VLAN architecture system  
A system in which a single VLAN architecture spans multiple VLAN transport protocols and technologies, including a method and system in which multiple different VLANs may be combined in a single...
6275890 Low latency data path in a cross-bar switch providing dynamically prioritized bus arbitration  
The present invention provides a cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus...
6272618 System and method for handling interrupts in a multi-processor computer  
A system and method for handling system management interrupts in a multi-processor computer is disclosed. When the computer enters system management mode, the method uses the registers of each...
6253304 Collation of interrupt control devices  
A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one...
6161170 Multiple processor, distributed memory computer with out-of-order processing  
A distributed memory computer architecture associates separate memory blocks with their own processors, each of which executes the same program. A processor fetching data or instructions from its...
6117180 Hardware-software co-synthesis of heterogeneous distributed embedded systems for low overhead fault tolerance  
Embedded systems employed in critical applications demand high reliability and availability in addition to high performance. Hardware-software co-synthesis is the process of partitioning an...
6119143 Computer system and method for load balancing with selective control  
A computerized method for load balancing in a geographically distributed or clustered system is disclosed. An arbiter assigns clients to nodes. The arbiter partitions clients into groups based on...
6112283 Out-of-order snooping for multiprocessor computer systems  
In some embodiments, a computer system includes nodes connected through conductors. At least some of the nodes each include memory and processing circuitry to receive snoop requests in a node...
6085307 Multiple native instruction set master/slave processor arrangement and method thereof  
A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In...
6032245 Method and system for interrupt handling in a multi-processor computer system executing speculative instruction threads  
In the system bus controller of a multi-processor system, apparatus is provided for selecting one of the processors to handle an interrupt. A mask is provided for each respective task being...
5978831 Synchronous multiprocessor using tasks directly proportional in size to the individual processors rates  
Multiprocessor architecture having advantages of both synchronous and asynchronous architectures. The multiprocessor (FIG. 10) comprises processors (300) operating in parallel and synchronously....
5920714 System and method for distributed multiprocessor communications  
In a tightly coupled communication scheme based on a common shared resource circuit having a plurality of shared information registers and adapted particularly to a multiprocessing system having 2...
5881303 Multiprocessing system configured to perform prefetch coherency activity with separate reissue queue for each processing subnode  
A computer system includes multiple processing nodes, each of which is divided into subnodes. Transactions from a particular subnode are performed in the order presented by that subnode. Therefore,...
5856921 Apparatus and method for intermodular communications using system bus controllers  
A system bus architecture for intermodular communications is disclosed. The system bus architecture comprises a backplane bus with associated memory and a plurality of control registers. A master...
5854938 Parallel processor apparatus in which data is divided in sequential stages  
A parallel processor apparatus, which enables a blocking work for assuring a bucket write/read performance with a storage quantity in an ordinary range so as to largely improve the bucket...
5852742 Configurable data processing pipeline  
A print data processing pipeline for use in a color electrophotographic printer optimizes print quality and minimizes memory usage by separately processing lossy and lossless print data. Lossy...
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