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8090928 |
Methods and apparatus for processing scalar and vector instructions
In one embodiment of the present invention, a processor includes a scalar computation unit; a vector co-processor coupled to the scalar computation unit; and one or more function-specific engines...
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8078804 |
Method and arrangement for cache memory management, related processor architecture
A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for...
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8069124 |
Combining speculative physics modeling with goal-based artificial intelligence
In one embodiment, the present invention includes a method for identifying a deformable object of a scene of a computer game that is visible by an artificial intelligence (AI) character of the...
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7971197 |
Automatic instruction set architecture generation
A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations...
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7908460 |
Method and apparatus for obtaining a scalar value directly from a vector register
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a...
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7895411 |
Physics processing unit
One embodiment of the invention sets forth a hardware-based physics processing unit (PPU) having unique architecture designed to efficiently generate physics data. The PPU includes a PPU control...
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7877582 |
Multi-addressable register file
A single register file may be addressed using both scalar and SIMD instructions. That is, subsets of registers within a multi-addressable register file according to the illustrative embodiments,...
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7831804 |
Multidimensional processor architecture
A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which...
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7739480 |
Method and apparatus for obtaining a scalar value directly from a vector register
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a...
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7739479 |
Method for providing physics simulation data
A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data.
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7676647 |
System and method of processing data using scalar/vector instructions
A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code...
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7661006 |
Method and apparatus for self-healing symmetric multi-processor system interconnects
A computer implemented method, apparatus, and computer program product for managing symmetric multiprocessor interconnects. The process identifies functional communication connections between each...
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7457938 |
Staggered execution stack for vector processing
In one embodiment, the present invention includes a method for executing an operation on low order portions of first and second source operands using a first execution stack of a processor and...
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7437521 |
Multistream processing memory-and barrier-synchronization method and apparatus
A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that...
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7350057 |
Scalar result producing method in vector/scalar system by vector unit from vector results according to modifier in vector instruction
Described herein is a method and system for executing instructions. The system comprises a scalar unit for executing scalar instructions each defining a single value pair; a vector unit for...
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7334110 |
Decoupled scalar/vector computer architecture system and method
In a computer system having a scalar processing unit and a vector processing unit, wherein the vector processing unit includes a vector dispatch unit, a system and method of decoupling operation of...
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7305540 |
Method and apparatus for data processing
Methods and apparatuses for a data processing system are described herein. In one aspect of the invention, an exemplary apparatus includes a chip interconnect, a memory controller for controlling...
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7254696 |
Functional-level instruction-set computer architecture for processing application-layer content-service requests such as file-access requests
A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC...
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7032101 |
Method and apparatus for prioritized instruction issue queue in a processor
An apparatus and method in a high performance processor for issuing instructions, comprising; a classification logic for sorting instructions in a number of priority categories, a plurality of...
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7028145 |
Protocol processor intended for the execution of a collection of instructions in a reduced number of operations
Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor...
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6963341 |
Fast and flexible scan conversion and matrix transpose in a SIMD processor
The present invention provides efficient ways to implement scan conversion and matrix transpose operations using vector multiplex operations in a SIMD processor. The present method provides a very...
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6857061 |
Method and apparatus for obtaining a scalar value directly from a vector register
A method and apparatus for obtaining a scalar value from a vector register for use in a mixed vector and scalar instruction, including providing a vector in a vector register file, and embedding a...
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6839828 |
SIMD datapath coupled to scalar/vector/address/conditional data register file with selective subpath scalar processing mode
There is provided a processor designed to operate in a plurality of modes for processing vector and scalar instructions. Register files are each for storing scalar and vector data and address...
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6839889 |
Mixed hardware/software architecture and method for processing xDSL communications
A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The...
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6734874 |
Graphics processing unit with transform module capable of handling scalars and vectors
A method, apparatus and article of manufacture are provided for handling both scalar and vector components during graphics processing. To accomplish this, vertex data is received in the form of...
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6665774 |
Vector and scalar data cache for a vector multiprocessor
A common scalar/vector data cache apparatus and method for a scalar/vector computer. One aspect of the present invention provides a computer system including a memory. The memory includes a...
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6609189 |
Cycle segmented prefix circuits
The poor scalability of existing superscalar processors has been of great concern to the computer engineering community. In particular, the critical-path delays of many components in existing...
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6530011 |
Method and apparatus for vector register with scalar values
A method and an apparatus for implementing mixed scalar and vector values in a digital processing system. In one embodiment, a digital processing system, which contains processing unit and...
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6219775 |
Massively parallel computer including auxiliary vector processor
A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing...
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6212617 |
Parallel processing method and system using a lazy parallel data type to reduce inter-processor communication
A parallel programming system provides a lazy collection oriented data type that reduces inter-processor communication in programs executed on parallel computers. The lazy collection oriented data...
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6141673 |
Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions
A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus...
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6106573 |
Apparatus and method for tracing microprocessor instructions
A microprocessor implements an instruction tracing mechanism that saves the state of the microprocessor without special hardware. Prior to the execution of a traced instruction, a trace microcode...
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6073158 |
System and method for processing multiple received signal sources
A system and method for time slicing multiple received data streams utilizing multiple processors in such a manner as to ensure that all processors are running at full capability and are...
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6055620 |
Apparatus and method for system control using a self-timed asynchronous control structure
A control apparatus and method is provided for controlling operations of functional units in systems. The control apparatus and method implement a set of operations that can include dependencies...
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6052769 |
Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction
A method comprises decoding a single instruction having a first operand identifying a plurality of bytes of packed data and a second operand identifying a corresponding plurality of byte masks....
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6044453 |
User programmable circuit and method for data processing apparatus using a self-timed asynchronous control structure
A programmable circuit and method for a data processing apparatus is provided that allows an entire instruction or instruction set to be modified. According to the present invention, the...
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5991865 |
MPEG motion compensation using operand routing and performing add and divide in a single instruction
A routable operand and selectable operation processor multimedia extension unit is employed to motion compensate MPEG video using improved vector processing. A vector processing unit executes an...
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5935230 |
Multiprocessor arrangement including bus arbitration scheme involving plural CPU clusters that address each other as "phantom" CPUs
At least two clusters of CPUs are present in a multiprocessor computer system. Each CPU cluster has a given number of CPUs, each CPU having an associated ID such as an ID number. An additional ID...
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5819054 |
Storage system realizing scalability and fault tolerance
A storage system to be connected to a large-scale computer includes a plurality of first logical units connected to a host device, a plurality of second logical units connected to a storage device,...
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5742842 |
Data processing apparatus for executing a vector operation under control of a master processor
A slave processor for executing for example a vector operation is connected to a master processor. A vector length for a vector operation set to the slave processor can be changed without...
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5598571 |
Data processor for conditionally modifying extension bits in response to data processing instruction execution
A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single...
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5561808 |
Asymmetric vector multiprocessor composed of a vector unit and a plurality of scalar units each having a different architecture
A vector multiprocessor comprises a plurality of scalar units for executing a scalar instruction and a vector unit for executing a vector instruction, and processes, through a single vector unit,...
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5517666 |
Program controlled processor wherein vector distributor and vector coupler operate independently of sequencer
A program controlled processor comprises a scalar processing unit 101 for normal data (=scalar) operations and branch processing, a plurality of vector processing units 102 of identical structure,...
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5475849 |
Memory control device with vector processors and a scalar processor
A memory control unit connected to a scalar processor having a buffer for storing a copy of block data of a main storage and a vector processor having a store requester for writing data into the...
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5430884 |
Scalar/vector processor
The present invention is an improved high performance scalar/vector processor. In the preferred embodiment, the scalar/vector processor is used in a multiprocessor system. The scalar/vector...
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5418973 |
Digital computer system with cache controller coordinating both vector and scalar operations
A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit, and a cache controller unit. The...
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5319791 |
System for predicting memory fault in vector processor by sensing indication signal to scalar processor to continue a next vector instruction issuance
A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the...
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5261113 |
Apparatus and method for single operand register array for vector and scalar data processing operations
In a data processing system in which a processing unit can execute both scalar and vector instructions, the use of a single operand register file to store both the scalar operation operands and the...
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5247691 |
System for releasing suspended execution of scalar instructions following a wait instruction immediately upon change of vector post pending signal
A data processing system containing a scalar unit, a vector unit, and a storage. The scalar unit receives scalar instructions and vector instructions, carries out scalar data processing in...
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5226171 |
Parallel vector processing system for individual and broadcast distribution of operands and control information
A parallel processing system utilizes a plurality of simultaneously operable arithmetic units to provide matrix-vector products, with each of the arithmetic units implementing the matrix-vector...
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