|
Match
|
Document |
Document Title |
|
|
7620776 |
Method, apparatus, and computer program product for a cache coherency protocol state that predicts locations of modified memory blocks
A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast remote requests to reduce the latency to access data from local nodes and to...
|
|
|
7614059 |
System and method for the discovery and usage of local resources by a mobile agent object
A method is presented for a mobile agent object to discover services available in a host-computing environment. According to an embodiment of this method, the mobile agent object requests a service...
|
|
|
7600095 |
Executing scatter operation to parallel computer nodes by repeatedly broadcasting content of send buffer partition corresponding to each node upon bitwise OR operation
Executing a scatter operation on a parallel computer includes: configuring a send buffer on a logical root, the send buffer having positions, each position corresponding to a ranked node in an...
|
|
|
7596705 |
Automatically controlling processor mode of multi-core processor
An apparatus for controlling a power management mode of a multi-core processor in a computer system includes a monitoring unit configured for monitoring conditions relating to the power management...
|
|
|
7594233 |
Processing thread launching using volunteer information
A method of and computer system for selecting a processor of a computer system on which to launch a processing thread is described. Each processor load is compared with a volunteer load of a...
|
|
|
7594045 |
Memory control apparatus for digital signal processing
A memory control apparatus and method for operating a plurality of digital signal processors (DSPs) using a single memory slot and buffer are provided. Exemplary embodiments provide at least one...
|
|
|
7584369 |
Method and apparatus for monitoring and controlling heat generation in a multi-core processor
The disclosed methodology and apparatus may control heat generation in a multi-core processor. In one embodiment, each processor core includes a temperature sensor that reports temperature...
|
|
|
7581081 |
Systems and methods for software extensible multi-processing
A system for processing applications includes processor nodes and links interconnecting the processor nodes. Each node includes a processing element, a software extensible device, and a...
|
|
|
7581079 |
Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructions
A shared memory network for communicating between processors using store and load instructions is described. A new processor architecture which may be used with the shared memory network is also...
|
|
|
7552439 |
System and method to allow non-deterministic execution in a process control system
A method includes receiving at least one process control value from a deterministic process control environment according to an execution cycle of the deterministic process control environment. The...
|
|
|
7533382 |
Hyperprocessor
A hyperprocessor includes a control processor controlling tasks executed by a plurality of processor cores, each of which may include multiple execution units, or special hardware units. The...
|
|
|
7526456 |
Method of operation for parallel LCP solver
A method of operating a Linear Complementarity Problem (LCP) solver is disclosed, where the LCP solver is characterized by multiple execution units operating in parallel to implement a competent...
|
|
|
7516301 |
Multiprocessor computing systems with heterogeneous processors
Heterogeneous processors can cooperate for distributed processing tasks in a multiprocessor computing system. Each processor is operable in a “compatible” mode, in which all processors within a...
|
|
|
7503046 |
Method of obtaining interleave interval for two data values
A method of determining an interleave pattern for n lots of A and y lots of B, when n plus y equals a power of two such that the expression 2 z −n may be used to represent the value of y,...
|
|
|
7490219 |
Counter counts valid requests based on a judgment in a system having a plurality of pipeline processors
In the present invention, in order that a busy judgment of a register can be made without fail and without increasing the number of hardware resources for storing a request into the register...
|
|
|
7487271 |
Method and apparatus using buffer pools and arrays of buffer pointers for sharing memory in a multiprocessor system
A multiprocessor system ( 100 ) for sharing memory has a memory ( 102 ), and two or more processors ( 104 ). The processors are programmed to establish ( 202 ) memory buffer pools between the...
|
|
|
7487221 |
Network system, distributed processing method and information processing apparatus
A network system by which the processing speed of the entire system can be enhanced. The network system includes a number of information processing apparatus connected to each other through a...
|
|
|
7478031 |
Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information
A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an...
|
|
|
7466316 |
Apparatus, system, and method for distributing work to integrated heterogeneous processors
An integrated circuit includes at least two different types of processors, such as a graphics processor and a video processor. At least one operation is commonly by supported by two different types...
|
|
|
7454502 |
System for transferring standby resource entitlement
A method for transferring entitlement to standby resources between respective computers. Standby resources are made available at a destination computer by rendering unavailable corresponding...
|
|
|
7446773 |
Apparatus, system, and method for integrated heterogeneous processors with integrated scheduler
An integrated circuit includes at least two different types of processors. The integrated circuit includes an integrated host and associated scheduler. At least one operation is supported by two or...
|
|
|
7441106 |
Distributed processing in a multiple processing unit environment
Method and apparatus for performing distributed processing in a multi-processing unit environment. A first processing unit modifies a complex operation to provide an operational request packet...
|
|
|
7436559 |
Load assignment in image processing by parallel processing
In image processing carried out by means of repeated execution of process set which includes N unit processes (where N is an integer equal to 3 or greater), prior to execution of the process...
|
|
|
7428210 |
Fail over method and a computing system having fail over function
Loads on a plurality of computers are made uniform after a fail over, and resource competition is prevented. Loads of nodes ( 1 to 4 ) in a cluster ( 100 ) are obtained, taking-over information...
|
|
|
7426500 |
Parallel computer architecture of a cellular type, modifiable and expandable
This processing is distributed among number of simple hexagonal units distributed in a honeycomb layer, consisting of a central hexagram surrounded by six receiving cells, each representing an...
|
|
|
7426182 |
Method of managing signal processing resources
A method of setting up a new call in a signal processor includes selecting a signal processor that has sufficient bandwidth to open a new channel while assuming that the new channel and any open...
|
|
|
7424581 |
Host memory interface for a parallel processor
A memory interface for a parallel processor which has an array of processing elements and can receive a memory address and supply the memory address to a memory connected to the processing...
|
|
|
7415595 |
Data processing without processor core intervention by chain of accelerators selectively coupled by programmable interconnect network and to memory
A programmable digital signal processor includes a plurality of memory units, a plurality of accelerator units and a processor core. The digital signal processor also includes a programmable...
|
|
|
7401333 |
Array of parallel programmable processing engines and deterministic method of operating the same
The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least...
|
|
|
7398368 |
Atomic operation involving processors with different memory transfer operation sizes
Atomic operations may be implemented on a processor system having a main memory and two or more processors including a power processor element (PPE) and a synergistic processor element (SPE) that...
|
|
|
7395082 |
Method and system for handling events in an application framework for a wireless device
Methods and systems for application framework development for wireless devices are provided herein. Aspects of the method may include acquiring an MMI event from an MMI event queue within the MMI...
|
|
|
7386714 |
Transmitting data from a single storage unit between multiple processors during booting
An electronic control unit includes a main microcomputer and a sub-microcomputer. Both the microcomputers include buffers for initialization and buffers for normal processing. At the time of...
|
|
|
7386619 |
System and method for allocating communications to processors in a multiprocessor system
In a multiprocessor-system, a system and method assigns communications to processors, processes, or subsets of types of communications to be processed by a specific processor without using a...
|
|
|
7383423 |
Shared resources in a chip multiprocessor
In one embodiment, a node comprises a plurality of processor cores and a node controller configured to receive a first read operation addressing a first register. The node controller is configured...
|
|
|
7380102 |
Communication link control among inter-coupled multiple processing units in a node to respective units in another node for request broadcasting and combined response
A data processing system includes a first processing node and a second processing node. The first processing node includes a plurality of first processing units coupled to each other for...
|
|
|
7380039 |
Apparatus, method and system for aggregrating computing resources
A system for executing applications designed to run on a single SMP computer on an easily scalable network of computers, while providing each application with computing resources, including...
|
|
|
7363095 |
Audio processing system
The invention relates to an audio processing system 1 . In order to improve the audio processing, the system comprises at least one audio processing component 11, 12, 13 with a group of...
|
|
|
7362762 |
Distributed packet processing with ordered locks to maintain requisite packet orderings
Sequences of items may be maintained using ordered locks. These items may correspond to anything, but using ordered locks to maintain sequences of packets, especially for maintaining requisite...
|
|
|
7356819 |
Task distribution
Methods, signals, devices and systems are provided for matching tasks with processing units. A region within a multi-faceted task space is allocated to a processing unit. A point in the...
|
|
|
7350209 |
System and method for application performance management
An improved method and system for complex and integrated application performance management which tracks end-to-end computer resource consumption of a first business application workflow in an...
|
|
|
7337306 |
Executing conditional branch instructions in a data processor having a clustered architecture
There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control...
|
|
|
7308558 |
Multiprocessor data processing system having scalable data interconnect and data routing mechanism
The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that...
|
|
|
7302548 |
System and method for communicating in a multi-processor environment
A method for communicating in a multi-processor environment is provided that includes generating a bit at an originating processor associated with a message to be communicated to a destination...
|
|
|
7299467 |
Method and system for minimizing memory access latency in a computer system
A computer system includes a plurality of nodes coupled together wherein each node may comprise a processor and memory. The system may also include a plurality of software objects usable by any of...
|
|
|
7299427 |
Radio prototyping system
A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide...
|
|
|
7299100 |
Digital signal processing apparatus and digital signal processing method
Herein disclosed is a digital signal processing apparatus comprising: input means for inputting a plurality of acoustic signals from an external outputting device; a plurality of digital signal...
|
|
|
7272664 |
Cross partition sharing of state information
A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor...
|
|
|
7254695 |
Coprocessor processing instructions in turn from multiple instruction ports coupled to respective processors
A coprocessor instruction interface is described which provides a flexible degree of coupling with a host control processor. Specific methods are defined for architectures to make use of multiple...
|
|
|
7254694 |
Processors interconnect fabric with relay broadcasting and accumulation of partial responses
A data processing system includes a plurality of processing units each having a respective point-to-point communication link with each of multiple others of the plurality of processing units but...
|
|
|
7249357 |
Transparent distribution and execution of data in a multiprocessor environment
Apparatus, methods, data structures, and systems are provided for subdividing input data associated with a first software program into job quanta, wherein each job quantum is operable to be...
|