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7493478 |
Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft...
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7472051 |
Dependable microcontroller, method for designing a dependable microcontroller and computer program product therefor
A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault...
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7447880 |
Processor with internal memory configuration
A processor comprises an arithmetic unit for processing operands, a register memory for storing operands with a register memory space and a register memory configuration unit. The register memory...
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7418583 |
Data dependency detection using history table of entry number hashed from memory address
A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least...
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7398376 |
Instructions for ordering execution in pipelined processes
Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Hardware, in conjunction with compiler directives, allows memory...
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7386710 |
Methods and apparatus for scalable array processor interrupt detection and response
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution...
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7254689 |
Decompression of block-sorted data
In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a...
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7191314 |
Reconfigurable CPU with second FSM control unit executing modifiable instructions
A reconfigurable control structure for CPUs comprises a first control unit with a first basic instruction set associated therewith, and a second control unit, with a second instruction set...
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7124280 |
Execution control apparatus of data driven information processor for instruction inputs
An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the a number of inputs of an instruction; a waiting data storage region that...
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7103759 |
Microcontroller architecture supporting microcode-implemented peripheral devices
Methods and apparatus for creating microcode-implemented peripheral devices for a microcontroller core formed in a monolithic integrated circuit. The microcontroller core has a control store for...
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7103758 |
Microcontroller performing safe recovery from standby mode
A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is...
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7000098 |
Passing a received packet for modifying pipelining processing engines' routine instructions
In one embodiment, a method is provided. The method of this embodiment includes generating, by a processor that includes a plurality of processing engines capable of executing program instructions,...
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6986027 |
Universal load address/value prediction using stride-based pattern history and last-value prediction in a two-level table scheme
This invention is a method and system for hybrid prediction of load addresses and/or values. The new scheme for value prediction provides prediction based on last values and strides, as well as...
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6925554 |
Method of programming USB microcontrollers
An apparatus comprising a microcontroller configured to (i) send or receive data over one or more data lines when in a first mode and (ii) be programmed through said data lines when in a second mode.
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6920551 |
Configurable processor system
A programmable integrated circuit can be designed to emulate, on demand, one of several commonly used microprocessors. It contains a configurable instruction processing unit and a superset datapath...
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6904511 |
Method and apparatus for register file port reduction in a multithreaded processor
Techniques for thread-based register file access by a multithreaded processor are disclosed. The multithreaded processor determines a thread identifier associated with a particular processor...
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6880074 |
In-line code suppression
Processor overhead is reduced and processor performance, particularly processing speed and power savings, is improved, allowing real-time processor restarts, by skipping operational codes (opcodes)...
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6865669 |
Methods for optimizing memory resources during initialization routines of a computer system
Methods for optimizing of memory resources during an initialization routine of a computer system which prepares the computer system for loading of an operating system is disclosed. One exemplary...
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6862676 |
Superscalar processor having content addressable memory structures for determining dependencies
A superscalar processor having a content addressable memory structure that transmits a first and second output signal is presented. The superscalar processor performs out of order processing on an...
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6854051 |
Cycle count replication in a simultaneous and redundantly threaded processor
A pipelined, simultaneous and redundantly threaded (“SRT”) processor comprising, among other components, load/store units configured to perform load and store operations to or from data...
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6842848 |
Method and apparatus for token triggered multithreading
Techniques for token triggered multithreading in a multithreaded processor are disclosed. An instruction issuance sequence for a plurality of threads of the multithreaded processor is controlled by...
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6820194 |
Method for reducing power when fetching instructions in a processor and related apparatus
In one disclosed embodiment an instruction loop having at least one instruction is identified. For example, each instruction can be a VLIW packet comprised of several individual instructions. The...
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6810477 |
Programmable controller including instruction decoder for judging execution/non-execution based on the state of contact points after execution of a preceding sequence program
An instruction decode section judges execution/non-execution according to a state of a contact point of the last sequence program stored in a conductive/non-conductive information storage section...
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6804772 |
Dynamic field patchable microarchitecture
A microprocessor memory architecture including a read-only memory (ROM) with programmed microcode and a random access memory (RAM) capable of storing microcode and one or more data bits used for...
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6779102 |
Data processor capable of executing an instruction that makes a cache memory ineffective
A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the...
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6772276 |
Flash memory command abstraction
Flash memory device capable of interpreting a write cycle and one or more subsequent write cycles as a generic command that includes one or more specific flash memory commands. The flash memory...
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6754807 |
System and method for managing vertical dependencies in a digital signal processor
An apparatus for managing vertical dependencies between instructions in first and second instruction pipelines includes: 1) identifier (ID) reclaim circuitry for determining a sequential set of...
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6742107 |
Dynamically configured processing of composite stream input data using next conversion determining state transition table searched by converted input data
A table storing a state transition rule is arranged in a memory. By referencing the table based on input data, the process to be performed for the input data is determined and executed....
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6732258 |
IP relative addressing
A processor supports instruction pointer (IP) relative addressing in at least one operating mode of the processor. For example, in some implementations, IP relative addressing is supported in an...
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6708235 |
Multi-modem implementation with host based and digital signal processor based modems
A plurality of modems or modem types can run on a host processor, a digital signal processor or both, either concurrently or selectively. Modules of more than one modem program can be swapped in...
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6684323 |
Virtual condition codes
The present invention utilizes a “virtual” condition code (VCC) which can control the instruction sequence in a microprocessor. The virtual condition code is stored in an internal,...
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6629192 |
Method and apparatus for use of a non-volatile storage management system for PC/AT compatible system firmware
In one embodiment, the invention is an apparatus. The apparatus includes a BIOS embodied in a non-volatile storage device. The apparatus also includes a non-volatile storage manager embodied in the...
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6625725 |
Speculative reuse of code regions
A speculative code reuse mechanism includes a reuse buffer, a main processing core and a reuse checking core. The reuse buffer includes inputs and outputs of previously executed instances of code...
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6606704 |
Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support...
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6574747 |
Extensible execute in place (XIP) architecture and related methods
A system implementing an execute-in-place (XIP) architecture is presented comprising a plurality of XIP regions. To facilitate execute-in-place functionality across the multiple XIP regions, a...
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6560698 |
Register change summary resource
A microcontroller provides a register change summary resource for summarizing register changes. Selected system registers within each resource are coupled to bits in resource change registers of...
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6535984 |
Power reduction for multiple-instruction-word processors with proxy NOP instructions
A method of optimizing assembly code of a VLIW processor ( 10 ) or other processor that uses multiple-instruction words ( 20 ), each of which comprise instructions to be executed on different...
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6460129 |
Pipeline operation method and pipeline operation device to interlock the translation of instructions based on the operation of a non-pipeline operation unit
A pipeline operation method and a pipeline operation device in which an operation result of an operation unit can be effectively written to a register. In the pipeline operation method and the...
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6442672 |
Method for dynamic allocation and efficient sharing of functional unit datapaths
The invention is a processing method and a processor architecture which contains multiple processors on the same silicon but which does not make a fixed compromise by statically assigning...
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6427207 |
Result forwarding cache
An apparatus is presented for expediting the execution of dependent micro instructions in a pipeline microprocessor having design characteristics-complexity, power, and timing—that are not...
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6427202 |
Microcontroller with configurable instruction set
An embeddable microcontroller is provided. The microcontroller has program memory for storing instructions. An instruction decoder feteches instructions, decodes them, and forwards them to an...
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6374312 |
System for dedicating a host processor to running one of a plurality of modem programs and dedicating a DSP to running another one of the modem programs
A plurality of modems or modem types can run on a host processor, a digital signal processor or both, either concurrently or selectively. Modules of more than one modem program can be swapped in...
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6363474 |
Process switching register replication in a data processing system
In a data processing system that includes a safe store buffer containing valid copies of all registers, processor transitions from a higher security routine to a lower security routine can be...
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6341346 |
Method for comparison between a pattern sequence and a variable length key
A method is disclosed for comparing a pattern sequence with a variable length key. A first bit of this sequence is identified by a pointer, the length and the location of the key are identified by...
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6338136 |
Pairing of load-ALU-store with conditional branch
An apparatus and method are provided for executing a compare-and-jump operation in a pipeline microprocessor. Typically, the compare-and-jump operation is specified by two micro instructions. The...
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6317803 |
High-throughput interconnect having pipelined and non-pipelined bus transaction modes
A high throughput memory access port is provided. The port includes features which provide higher data transfer rates between system memory and video/graphics or audio adapters than is possible...
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6308256 |
Secure execution of program instructions provided by network interactions with processor
A CPU is provided with an ability to modify its operation in accordance with an encryption key. When a program is compiled, the program is modified in order that execution may be performed with the...
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6301651 |
Method and apparatus for folding a plurality of instructions
The present invention provides a stack machine for executing a plurality of instructions one by one. The stack machine comprises an operation folder and an execution unit. The operation folder is...
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6292888 |
Register transfer unit for electronic processor
A processing system has an instruction processor (IP), register files for storing data to be processed by the IP, such as a thread context, and a register transfer unit (RTU) connected to the...
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6266767 |
Apparatus and method for facilitating out-of-order execution of load instructions
A processor (100) includes a preload queue (160) for storing a plurality of preload entries. Each preload entry is associated with a preload instruction and includes the address and byte count...
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