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7376811 Method and apparatus for performing computations and operations on data using data steering  
A data processing system architecture is based upon a hardware engine that includes a plurality of functional units and data routing units that interconnect the functional units. The hardware...
7254689 Decompression of block-sorted data  
In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a...
7103758 Microcontroller performing safe recovery from standby mode  
A microcontroller has a memory storing a program with an instruction that causes the microcontroller's central processing unit to enter a standby mode, in which data output from the memory is...
6957326 Methods and apparatuses for executing threads  
A first process thread is executed by a RISC processor using data in a first register set. While executing the first process thread, a second register set is loaded with data associated with a...
6948005 Peripheral device for programmable controller  
A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying...
6825843 Method and apparatus for loop and branch instructions in a programmable graphics pipeline  
A method and apparatus for executing loop and branch program instructions in a programmable graphics shader. The programmable graphics shader converts a sequence of instructions comprising a...
6745316 Data processing system  
A data processing system is disclosed. The system includes a control command storage device, a data storage device, an address pointer, a multi-level signal decoder and a data processing unit. The...
6715065 Micro program control method and apparatus thereof having branch instructions  
In an information processing apparatus which executes micro programs having branch instructions, two micro instructions are read at once, each of which instructions comprises either a field for...
6560698 Register change summary resource  
A microcontroller provides a register change summary resource for summarizing register changes. Selected system registers within each resource are coupled to bits in resource change registers of...
6496926 Computer-implemented paramaterless language with exception handler  
A non-traditional computing machine implements a parameterless computer language that operates without operands and without linear addressing of code or data. A code space having multiple...
6466828 Device controller with intracontroller communication capability, conveying system using such controllers for controlling conveying sections and methods related thereto  
Featured is a device controller in a system having a multiplicity of such controllers and a conveying system and method for controlling a multiplicity of devices using such controllers. Each...
6438680 Microprocessor  
When a decision circuit ( 217 ) incorporated in a control circuit ( 21 ) in an instruction decode unit ( 2 ) in a microprocessor ( 1 ) decides that an integer operation unit ( 4 ) can not execute a...
6341328 Method and apparatus for using multiple co-dependent DMA controllers to provide a single set of read and write commands  
A microcomputer incorporates a pair of DMA controllers that are co-dependently operated to read and write common data blocks to two peripheral devices. In an exemplary embodiment of the invention,...
6308254 Processing instructions of an instruction set architecture by executing hierarchically organized snippets of atomic units of primitive operations  
A processor is provided with a datapath and control logic to control the datapath to selectively execute a number of hierarchically organized primitive operations to effectuate execution of user...
6263429 Dynamic microcode for embedded processors  
A method of compressing programs, especially those used in embedded systems, is provided which allows greater program compression without significantly degrading system performance. The method...
6230264 Parameterless language in a machine for implementation thereof  
A non-traditional computing machine having no operands and no linear addressing of code or data is disclosed. A code space having multiple dimensions contains programmed instructions each having a...
6112296 Floating point stack manipulation using a register map and speculative top of stack values  
A floating point unit capable of executing multiple instructions in a single clock cycle using a central window and a register map is disclosed. The floating point unit comprises: a plurality of...
6105125 High speed, scalable microcode based instruction decoder for processors using split microROM access, dynamic generic microinstructions, and microcode with predecoded instruction information  
A microcode based decoder circuit for microprocessors that uses fast access tables to decode instructions. The pointers to the tables are generated directly from the instruction prefetch buffers....
6058467 Standard cell, 4-cycle, 8-bit microcontroller  
An 8051 instruction set compatible microcontroller utilizing four or less clock cycles per machine cycle. The microcontroller is designed utilizing standard hardware design language techniques...
6035394 System for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallel  
One aspect of the invention relates to a method for operating a superscalar processor having an instruction cache, a sequencing unit, a load/store unit, a cache, an architectural register file and...
6026489 Signal processor capable of executing microprograms with different step sizes  
A signal processor stores at least one microprogram having m steps in total smaller in number than n steps which are to be executed within one sampling repetition period. A count corresponding to...
6018798 Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle  
A floating point unit capable of executing multiple instructions in a single clock cycle using a central window and a register map is disclosed. The floating point unit comprises: a plurality of...
6016539 Datapath control logic for processors having instruction set architectures implemented with hierarchically organized primitive operations  
A new datapath control logic for processors with ISA implemented employing hierarchically organized primitive operations is disclosed. The new datapath control logic includes a primary control unit...
5887151 Method and apparatus for performing a modified prefetch which sends a list identifying a plurality of data blocks  
A method of prefetching data within a data storage system that includes at least two levels of data storage including a first level and a second level and that also includes an intelligent...
5634119 Computer processing unit employing a separate millicode branch history table  
A computer processing system includes a first memory that stores instructions belonging to a first instruction set architecture and a second memory that stores instructions belonging to a second...
5530889 Hierarchical structure processor having at least one sub-sequencer for executing basic instructions of a macro instruction  
A hierarchical structure processor including a memory for storing processing instruction code data described sequentially; a main CPU for fetching and decoding the processing instruction code data...
5394558 Data processor having an execution unit controlled by an instruction decoder and a microprogram ROM  
A data processor in which, when two primitive instructions are decoded by instruction decoders, a microprogram ROM is not used under the control of a selector, and the two primitive instructions...
5241637 Data processor microsequencer having multiple microaddress sources and next microaddress source selection  
A data processor having a microsequencer which reduces power consumption selectively activates instruction decode units and a microcode sequence control memory unit. The microsequencer has an...
5235686 Computer system having mixed macrocode and microcode  
A computer system uses microcode subroutines to execute complex macroinstructions. Each macroinstruction is used to index a table. Simple macroinstructions have a single microinstruction...
5101344 Data processor having split level control store  
A data processor having a split level control store structure, which partitions program memory into a macrocode portion and a microcode portion. The data processor contains two distinct machines, a...
5034879 Programmable data path width in a programmable unit having plural levels of subinstruction sets  
A processor is disclosed having two levels of subinstructions, with the processor data bus being selectable as either a 16 bit or 32 bit wide bus under nanoprogram control.
4975837 Programmable unit having plural levels of subinstruction sets where a portion of the lower level is embedded in the code stream of the upper level of the subinstruction sets  
A processor has two levels of subinstructions, each stored in its own memory with the lower level memory containing only a limited set of such lower level instructions with the rest of the lower...
4928223 Floating point microprocessor with directable two level microinstructions  
A microprocessor integrator circuit includes split nanocode memories which enables simultaneous execution of an arithmetic operation and an operand fetch for maximizing through-put. The circuit...
4901235 Data processing system having unique multilevel microcode architecture  
A data processing system which includes a central processor unit which has an arithmetic logic unit (ALU) for performing fixed point arithmetic operations and a separate floating point unit (FPU)...
4901225 Processing apparatus with hierarchical structure for implementing a machine instruction  
According to a processing apparatus with a hierarchical structure, a machine instruction has a hierarchical structure of a task level operation code, a control structure level operation code, an...
4714991 Microprogram control apparatus having variable mapping between microinstruction control bits and generated control signals  
A data processing apparatus, which includes a microprogram control unit for producing control signals for the apparatus. Each microinstruction contains a number of control bits, and an address...
4550369 Apparatus and method for processing macroinstructions and microinstructions  
An instruction processing apparatus is composed of a main memory for storing user instructions and an instruction control section with a control store addressed by a user instruction read out from...
4467415 High-speed microprogram control apparatus with decreased control storage requirements  
A microprogrammed control apparatus includes a first control store for providing a first sequence of microinstructions and a second control store which includes first and second control store...
4360869 Control store organization for a data processing system  
A control store included in a data processing system for storing microinstructions in a plurality of microinstructions storage locations is organized in two parts, an upper bank and a lower bank....
4325121 Two-level control store for microprogrammed data processor  
A data processor having an execution unit and which includes a control means having a first and a second control store. The control means has an input for receiving a control store address. In...
4307445 Microprogrammed control apparatus having a two-level control store for data processor  
A microprogrammed control structure for an integrated circuit data processor which employs a two-level control store designated as a micro control store and nano control store. An instruction...
4251862 Control store organization in a microprogrammed data processing system  
A microprogram control system comprising first and second control memories each supplied with microinstructions. The microprogram control system usually executes a microinstruction of a prescribed...
4159519 Template family interfacing structure for providing a sequence of microinstructions to a pipelined microprogrammable data processing system  
In a microprogrammed pipelined data processing system, a template family interfacing structure sequences a plurality of templates to the pipelined system for control thereof, each template therein...
4032895 Electronic data processing computer  
An electronic computer comprising a first memory for recording instructions and data to be processed, a second memory for recording microinstructions and addressable by the instructions to provide...
4031521 Multimode programmable machines  
The disclosure teaches that a cyclable program loop can be alternatively used to selectively initiate subprograms or as a timing signal generator, the latter preferably in a maintenance mode of a...
4001788 Pathfinder microprogram control system  
A microprogram control system includes first and second control stores. The first is a pathfinder control store which is addressed initially by the operation code of a program instruction for read...
3990054 Microprogram organization techniques  
The disclosure describes improved microprogramming apparatus for a data processor. The improved apparatus includes a translating diode matrix which translates the operation code of a...
3980992 Multi-microprocessing unit on a single semiconductor chip  
This disclosure relates to a multimicroprocessor unit which is adapted for implementation in a single MOS semiconductor chip, which unit includes a plurality of sets of registers where each set...
3962685 Data processing system having pyramidal hierarchy control flow  
A data processing system employing a pyramidal hierarchical scheme of control flow in which instruction words identifying operations to be performed include defined portions prescribing the path of...
3886523 Micro program data processor having parallel instruction flow streams for plural levels of sub instruction sets  
A micro program system is disclosed which employs two levels of subinstruction sets. The first level of subinstructions, or micro instructions, is implemented by a second level of control...
Matches 1 - 50 out of 57 1 2 >