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7613907 |
Embedded software camouflage against code reverse engineering
Methods and apparatus for identifying a first flow control instruction in an executing program, the first instruction being associated with a first program address at which program execution will...
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7610476 |
Multiple control sequences per row of microcode ROM
Various embodiments of methods and systems for storing multiple groups of microcode operations and corresponding control sequences per row of microcode ROM are disclosed. In one embodiment, an...
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7602399 |
Method and apparatus for generating a pixel using a conditional IF—NEIGHBOR command
A device and method for controlling generation of a final pixel utilizes a conditional statement, referred to as an IF_NEIGHBOR statement, which when compiled, causes a programmable pixel shader to...
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7526638 |
Hardware alteration of instructions in a microcode routine
Processor logic gates are used to modify microcode instructions, while they are being executed. The results of previous operations are used by the hardware to modify subsequent instructions in a...
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7519799 |
Apparatus having a micro-instruction queue, a micro-instruction pointer programmable logic array and a micro-operation read only memory and method for use thereof
Embodiments of the present invention relate to high-performance processors, and more specifically, to processors that store all operation information associated with each instruction in a single...
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7506322 |
System and method of utilizing a hardware component to execute an interpretive language
A system and method of executing an interpretive language in a system having a processing component with native software processes and a memory component. A hardware component is coupled with the...
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7490230 |
Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor
A fetch director in a multithreaded microprocessor that concurrently executes instructions of N threads is disclosed. The N threads request to fetch instructions from an instruction cache. In a...
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7484077 |
Skipping unnecessary instruction by multiplex selector using next instruction offset stride signal generated from instructions comparison results
The present invention discloses an apparatus for removing unnecessary instruction and method thereof. The apparatus and operating method thereof include: a comparing circuit for comparing a...
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7480754 |
Assignment of queue execution modes using tag values
The queue execution mode is selected based on the unique tag that is assigned to the command. In one method embodiment a tag is assigned for each of several disc access commands sent by the host....
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7475227 |
Method of stalling one or more stages in an interlocked synchronous pipeline
A method of operating an integrated circuit including a pipeline and a method of stalling stages in the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are...
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7472259 |
Multi-cycle instructions
In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall...
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7441111 |
Controlled program execution by a portable data carrier
In a method for controlled program execution by a portable data carrier, the value of a status counter (ZZ) is altered during execution of each controlled section ( 36 .x) of an executed program (...
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7437537 |
Methods and apparatus for predicting unaligned memory access
In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the...
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7415602 |
Apparatus and method for processing a sequence of jump instructions
An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an...
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7412590 |
Information processing apparatus and context switching method
An information processing apparatus which, when executing a plurality of predetermined units of processing, executes the predetermined units of processing in parallel by a processor by switching...
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7404068 |
Single operation per-bit memory access
Mechanisms for performing per-bit operations in system memory in a single operation thereby obviating the need for semaphore mechanisms when performing per-bit operations. A processor accesses an...
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7401328 |
Software-implemented grouping techniques for use in a superscalar data processing system
A data processing system includes a grouping tool coupled to a processor. The grouping tool groups the stream of instructions such that each group of instructions has a dimensionless signature...
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7401211 |
Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor
In a multi-threaded processor, a long latency data dependent thread is flushed from the execution pipelines. Once the stalled thread is flushed, the non-stalling threads in the pipeline can...
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7398376 |
Instructions for ordering execution in pipelined processes
Ordering instructions for specifying the execution order of other instructions improve throughput in a pipelined multiprocessor. Hardware, in conjunction with compiler directives, allows memory...
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7389407 |
Central control system and method for using state information to model inflight pipelined instructions
A method and apparatus to control logic sections of a pipeline instruction processor is disclosed. A state machine is provided that models the flow of instructions through the pipeline. The state...
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7386710 |
Methods and apparatus for scalable array processor interrupt detection and response
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution...
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7376844 |
Countermeasure method for a microcontroller based on a pipeline architecture
A countermeasure method for a microcontroller that executes sequences of instructions. The instructions are executed according to a pipeline method. At least one waiting time is randomly introduced...
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7376818 |
Program translator and processor
Multiple instructions, specifying equivalent operations but designating different execution units, are stored beforehand on an instruction exchange table. First, a primary compiler compiles a...
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7373490 |
Emptying packed data state during execution of packed data instructions
A method in a computer system, one embodiment includes accessing a packed data instruction and generating a corresponding set of control bits to cause a processor to alter a top of stack to zero of...
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7370181 |
Single stepping a virtual machine guest using a reorder buffer
Embodiments of apparatuses, systems, and methods for single stepping a virtual machine guest using a reorder buffer are disclosed. In one embodiment, an apparatus includes a sequencer and a reorder...
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7370136 |
Efficient and flexible sequencing of data processing units extending VLIW architecture
A very long instruction word processor with sequence control. During each cycle the processor generates control signals to functional units based on the values in fields of an instruction. Each...
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7360062 |
Method and apparatus for selecting an instruction thread for processing in a multi-thread processor
The selection between instruction threads in a SMT processor for the purpose of interleaving instructions from the different instruction threads may be modified to accommodate certain processor...
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7353337 |
Reducing cache effects of certain code pieces
Cache memory interrupt service routines (ISRs) influence the replacement of necessary instructions of the instruction stream they interrupt; it is known as “instruction cache washing,” since...
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7349399 |
Method and apparatus for out-of-order processing of packets using linked lists
These and other aspects of the present invention will be better described with reference to the Detailed Description and the accompanying figures. A method and apparatus for out-of-order processing...
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7349398 |
Method and apparatus for out-of-order processing of packets
A method and apparatus for out-of-order processing of packets are described. In one embodiment, the method includes receiving packets in a global order, the packets being designated for different...
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7308593 |
Interlocked synchronous pipeline clock gating
An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively,...
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7305649 |
Automatic generation of a streaming processor circuit
A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation...
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7287146 |
Array-type computer processor
An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer...
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7278013 |
Apparatus having a cache and a loop buffer
Briefly, in accordance with one embodiment of the invention, a processor has a loop buffer and a cache that provides requested information to a processor core.
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7254689 |
Decompression of block-sorted data
In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a...
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7237100 |
Transaction redirection mechanism for handling late specification changes and design errors
Redefined hardware structured transactions and the associated responses in a data processing device are made user programmable. Three registers, a identifier register, a mask register and a...
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7231511 |
Microinstruction pointer stack including speculative pointers for out-of-order execution
Methods and apparatus, including computer program products, for a microinstruction pointer stack in a processor. A method executed in a processor includes executing microcode (μcode) addressed by...
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7231261 |
Method for automatically obtaining an operational sequence of processes and a tool for performing such method
In order to automatically calculate an operational sequence of processes that determine an output value from at least one input value, a multitude of processes (P 1 –P 8 ), whose inputs are...
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7213137 |
Allocation of processor bandwidth between main program and interrupt service instruction based on interrupt priority and retiring micro-ops to cache
The method and apparatus feature detecting an interrupt service request; storing into an instruction cache interrupt service instructions in response to detecting the interrupt service request; and...
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7213136 |
Apparatus and method for redundant zero micro-operation removal
A method and apparatus for redundant zero micro-operation removal. In one embodiment, the method includes the identification of a predetermined macro-instruction. Once identified, a value...
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7210129 |
Method for translating programs for reconfigurable architectures
A method for translating high-level languages to reconfigurable architectures is disclosed. The method includes building a finite automaton for calculation. The method further includes forming a...
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7203935 |
Hardware/software platform for rapid prototyping of code compression technologies
A method for code compression of a program, the method comprising separating code from data. Software transformations necessary to make address mappings between compressed and uncompressed space...
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7191321 |
Microengine for parallel processor architecture
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support...
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7159099 |
Streaming vector processor with reconfigurable interconnection switch
A re-configurable, streaming vector processor ( 100 ) is provided which includes a number of function units ( 102 ), each having one or more inputs for receiving data values and an output for...
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7155718 |
Method and apparatus to suspend and resume on next instruction for a microcontroller
In a computer system including at least one microcontroller, by suspending tasks after execution of particular instructions, such as a load-register-from-external-memory instruction, or when a...
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7149883 |
Method and apparatus selectively to advance a write pointer for a queue based on the indicated validity or invalidity of an instruction stored within the queue
A buffer mechanism for buffering microinstructions between a trace cache and an allocator performs a compacting operation by overwriting entries within a queue, known not to store valid...
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7127530 |
Command issuing apparatus for high-speed serial interface
In order to reduce load placed on a CPU (central processing unit) in providing SBP-2 (serial bus protocol 2) initiator capability, provided are a sequence control circuit activated by the CPU for...
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7120903 |
Data processing apparatus and method for generating the data of an object program for a parallel operation apparatus
An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of...
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7107361 |
Coupled computers and a method of coupling computers
The present invention provides coupled-type computers wherein a computer can be coupled with computers of the same structure easily, and can be coupled with other computers of the same structure in...
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7100028 |
Multiple entry points for system call instructions
A processor executes a system call instruction. The processor includes at least two registers in which target addresses may be stored, and selects the target address from one of the registers...
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