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9041513 System and method for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags  
A system and method is disclosed for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags. An RFID reader uses a Communicate With Data Logger Command to...
8997099 Virtualization event processing in a layered virtualization architecture  
Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and...
8959317 Processor and method for saving designated registers in interrupt processing based on an interrupt factor  
A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which...
8938608 Enabling portions of programs to be executed on system z integrated information processor (zIIP) without requiring programs to be entirely restructured  
A method for allowing portions of programs to be executed on a System z Integrated Information Processor (zIIP). A service call is inserted at the beginning of the zIIP eligible code to enable...
8935699 CPU sharing techniques  
Architectures and techniques for substantially maintaining performance of hyperthreads within processing cores of processors. One technique can include determining that a first thread is scheduled...
8935516 Enabling portions of programs to be executed on system z integrated information processor (zIIP) without requiring programs to be entirely restructured  
A system and computer program product for allowing portions of programs to be executed on a System z Integrated Information Processor (zIIP). A service call is inserted at the beginning of the...
8930682 Handling media streams in a programmable bit processor  
In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a...
8930638 Method and apparatus for supporting target-side security in a cache coherent system  
A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by...
8924697 Method for processing interrupt requests in a processor  
A method for processing interrupt requests in a processor is suitable for executing at least two threads in parallel, wherein an instruction pipeline is provided for each of the at least two...
8898442 Scenario-based process modeling for business processes including exception flow to handle an error in a task of the series of tasks  
Methods and systems for scenario-based process modeling are described. In one example embodiment, a system for scenario-based process modeling can include a scenario module, a deviations module, a...
8866826 Method and apparatus for dispatching graphics operations to multiple processing resources  
Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes...
8838864 Method and apparatus for improving the efficiency of interrupt delivery at runtime in a network system  
Processor affinity of an application/thread may be used to deliver an interrupt caused by the application/thread to a best processor at runtime. The processor to which the interrupt is delivered...
8813077 Virtualization event processing in a layered virtualization architecture  
Embodiments of apparatuses and methods for processing virtualization events in a layered virtualization architecture are disclosed. In one embodiment, an apparatus includes a event logic and...
8806104 Enabling virtualization of a processor resource  
In one embodiment, a processor includes an access logic to determine whether an access request from a virtual machine is to a device access page associated with a device of the processor and if...
8799929 Method and apparatus for bandwidth allocation mode switching based on relative priorities of the bandwidth allocation modes  
A system, apparatus, and method for allocation mode switching on an event-driven basis are described herein. The allocation mode switching method includes detecting an event, selecting a bandwidth...
8793689 Redundant multithreading processor  
A redundant multithreading processor is presented. In one embodiment, the processor performs execution of a thread and its duplicate thread in parallel and determines, when in a redundant...
8769250 Trap-based mechanism for tracking accesses of object class names  
In general, the invention relates to a method. The method includes receiving notification, which includes context information, of a trap. The method further includes accessing, based at least...
8762694 Programmable event-driven yield mechanism  
Method, apparatus, and system for a programmable event-driven yield mechanism. The mechanism may disrupt processing of a program to deliver a yield event. The event may be treated as a fault-like...
8752064 Optimizing communication of system call requests  
Provided herein is a method for optimizing communication for system calls. The method includes storing a system call for each work item in a wavefront and transmitting said stored system calls to...
8713294 Heap/stack guard pages using a wakeup unit  
A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes...
8689215 Structured exception handling for application-managed thread units  
Methods, data structures, instructions, and techniques for structured exception handling for user-level threads in a multi-threading system are provided. Registered filter routines may be...
8688964 Programmable exception processing latency  
A digital processor with programmable exception processing latency, may have a central processing unit (CPU) of a digital processor, an exception controller coupled with the CPU, and a control...
8677107 Apparatus and method for handling exception events  
Processing circuitry 4 has a plurality of exception states EL0-EL3 for handling exception events, the exception states including a base level exception state EL0 and at least one further level...
8661232 Register state saving and restoring  
In a data processing apparatus 1 having registers 6, when a state saving trigger event occurs while a result value of a data processing operation is still to be written to a destination register...
8656145 Methods and systems for allocating interrupts in a multithreaded processor  
A multithreaded processor capable of allocating interrupts is described. In one embodiment, the multithreaded processor includes an interrupt module and threads for executing tasks. The interrupt...
8615226 Data communication system, relay apparatus, and portable terminal apparatus  
There are provided: a data communication system, a relay apparatus, and a portable terminal apparatus in which when a mobile portable terminal apparatus such as a mobile telephone displays a...
8607035 Multi-core processing utilizing prioritized interrupts for optimization  
This invention relates to multi-core, multi-processing, factory multi-core and DSP multi-core. The nature of the invention is related to more optimal uses of a multi-core system to maximize...
8601443 Method and system for correlating trace data  
A computer program product comprises a computer useable medium. The computer useable medium has a computer readable program such that when the computer readable medium is executed on a computer,...
8601177 Dynamic allocation of a buffer across multiple clients in a threaded processor  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
8572357 Monitoring events and incrementing counters associated therewith absent taking an interrupt  
A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is...
8572573 Methods and apparatus for interactive debugging on a non-preemptible graphics processing unit  
Systems and methods are disclosed for performing interactive debugging of shader programs using a non-preemptible graphics processing unit (GPU). An iterative process is employed to repeatedly...
8572355 Support for non-local returns in parallel thread SIMD engine  
One embodiment of the present invention sets forth a method for executing a non-local return instruction in a parallel thread processor. The method comprises the steps of receiving, within the...
8549269 Method, apparatus or software for processing exceptions produced by an application program  
A method, apparatus and software is disclosed in which original exceptions issued by an application program are encoded as substitute exceptions with associated metadata identifying the original...
8539203 Multi-thread processor selecting threads on different schedule pattern for interrupt processing and normal operation  
In an exemplary aspect, the present invention provides a multi-thread processor including a plurality of hardware threads each of which generates an independent instruction flow, a thread...
8539209 Microprocessor that performs a two-pass breakpoint check for a cache line-crossing load/store operation  
A microprocessor breakpoint-checks a load/store operation specifying a load/store virtual address of data whose first and second pieces are within first and second cache lines. A queue of entries...
8527743 Simultaneous checking of plural exit conditions loaded in table subsequent to execution of wait instruction for jitter free exit  
A microprogrammable electronic device comprises a code memory storing a plurality of instructions. At least one instruction, when executed by the device, causes the device to enter into a wait...
8528000 Execution environment for data transformation applications  
The execution environment provides for scalability where components will execute in parallel and exploit various patterns of parallelism. Dataflow applications are represented by reusable dataflow...
8522000 Trap handler architecture for a parallel processing unit  
A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently...
8521995 Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode  
A method includes receiving control in a kernel mode via a ring transition from a user thread during execution of an unbounded transactional memory (UTM) transaction, updating a state of a...
8516231 Interrupt handling apparatus and method for equal-model processor and processor including the interrupt handling apparatus  
An interrupt support determining apparatus and method for an equal-model processor, and a processor including the interrupt support determining apparatus are provided. The interrupt support...
8516229 Two pass test case generation using self-modifying instruction replacement  
A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent...
8516224 Pipeline replay support for multicycle operations  
Instructions asserted in the instruction pipeline of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline of the...
8508782 Method of securing printers against malicious software  
A method for securing a computer device against malicious code, the method including the steps of: executing a computer program on the computer device, the computer device having a central...
8499140 Dynamically adjusting pipelined data paths for improved power management  
A design structure embodied in a machine readable, non-transitory storage medium used in a design process includes a system for dynamically varying the pipeline depth of a computing device. The...
8495606 Redundant exception handling code removal  
A system performs operations comprising creating a call graph for a program translated from source code, identifying redundant exception handling code in the program utilizing the call graph, and...
8493395 Hardware override of application programming interface programmed state  
A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override...
8489867 Monitoring events and incrementing counters associated therewith absent taking an interrupt  
A monitoring facility that is operable in two modes allowing compatibility with prior existing monitoring facilities. In one mode, in response to encountering a monitored event, an interrupt is...
8473728 Interrupt handling  
Techniques for handling interrupts of multiple instruction threads within a multi-thread processing environment. The techniques include: interleavingly fetching and issuing instructions of (i) a...
8464033 Setting a flag bit to defer event handling to one of multiple safe points in an instruction stream  
Methods and systems thereof for exception handling are described. An event to be handled is identified during execution of a code sequence. A bit is set to indicate that handling of the event is...
8447962 Gathering and scattering multiple data elements  
According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data...