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7634638 |
Instruction encoding for system register bit set and clear
An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the...
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7631125 |
Dynamically migrating channels
In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the...
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7617389 |
Event notifying method, event notifying device and processor system permitting inconsistent state of a counter managing number of non-notified events
An event notifying method notifies one or a plurality of events from a device to a processor by queuing to a queue in a processor system having one or a plurality of processors. A number of...
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7613912 |
System and method for simulating hardware interrupts
A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a “no operation” (or NOOP) instruction would normally be inserted....
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7613961 |
CPU register diagnostic testing
One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of...
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7613911 |
Prefetching exception vectors by early lookup exception vectors within a cache memory
An integrated circuit processor core 4 is provided with an instruction pipeline 20 along which program instructions advance. When an exception condition occurs part way through execution of a...
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7610475 |
Programmable logic configuration for instruction extensions
A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program...
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7607133 |
Interrupt processing control
A data processing system 2 supporting interrupt handling is provided with an interrupt controller 24 . The interrupt controller is responsive to save state data when interrupt processing is...
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7607042 |
Adjusting a processor operating parameter based on a performance criterion
Embodiments include a controller apparatus, a computerized apparatus, a device, an apparatus, and a method. A controller-apparatus includes a monitoring circuit for detecting a computational error...
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7603544 |
Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
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7600100 |
Instruction encoding for system register bit set and clear
An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates the...
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7596779 |
Condition management callback system and method of operation thereof
A condition management callback system and method for use with a processor employing a hierarchical register consolidation structure. In one embodiment, the system includes: (1) a condition...
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7594103 |
Microprocessor and method of processing instructions for responding to interrupt condition
A pipeline processing microprocessor includes a storage unit for storing instructions and a fetch unit for requesting and fetching an instruction from the instructions in the storage unit. Upon an...
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7581090 |
Interrupt control apparatus and method
When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register ( 452 ), a normal previous state register ( 453 ), and a normal...
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7577962 |
Routing exceptions to operating system subsystems
Techniques for routing exceptions to operating system subsystems are provided. In various embodiments, a software developer may add a global exception handler software component to an application....
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7577954 |
Process management method and image forming apparatus
Management of a process having a kernel mode and a user mode and executed on an operation system is performed by receiving a request for moving to a user system mode from a user process, and...
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7577961 |
Methods and apparatus for exception-based programming
In a programmed computer system, normal processing results generated by a called method are returned to one or more calling methods by an exception rather than by the more conventional single-type...
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7546446 |
Selective interrupt suppression
An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of interrupts at the instruction level. The apparatus includes translation...
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7539853 |
Handling interrupts in data processing of data in which only a portion of a function has been processed
A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the...
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7529917 |
Method and apparatus for interrupt handling during loop processing in reconfigurable coarse grained array
A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a...
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7522516 |
Exception handling system for packet processing system
An exception handling system for a packet processing system is described. In this exception handling system, there are several exception handlers. One of the exception handlers is selected based on...
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7523296 |
System and method for handling exceptions and branch mispredictions in a superscalar microprocessor
An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system...
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7516453 |
Binary translator with precise exception synchronization mechanism
A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where...
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7506207 |
Method and system using hardware assistance for continuance of trap mode during or after interruption sequences
A method, system, apparatus, and computer program product is presented for processing instructions. A processor is able to receive multiple types of interruptions while executing instructions, such...
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7502917 |
High speed memory cloning facility via a lockless multiprocessor mechanism
A processor chip that provides a dynamically selectable operating mode in which particular sequences of instructions are executed without an external interrupt. The processor chip comprises an...
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7496896 |
Accessing return values and exceptions
One or more new methods are added to existing object code. The existing object code includes a first method that is capable of producing a result. New code is added to the first method. The new...
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7487341 |
Handling address translations and exceptions of a heterogeneous resource of a processor using another processor resource
In one embodiment, the present invention includes a method for communicating a request for handling of a fault or exception occurring in an accelerator to a first instruction sequencer coupled...
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7475232 |
Performance of an in-order processor by no longer requiring a uniform completion point across different execution pipelines
A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a...
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7472051 |
Dependable microcontroller, method for designing a dependable microcontroller and computer program product therefor
A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault...
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7461386 |
Zero overhead exception handling
Apparatus and processes, including computer implemented processes, for managing exceptions throwable during execution of methods in one or more classes by a machine. Each method includes an...
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7451296 |
Method and apparatus for pausing execution in a processor or the like
A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET...
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7451298 |
Processing exceptions from 64-bit application program executing in 64-bit processor with 32-bit OS kernel by switching to 32-bit processor mode
One embodiment of the present invention provides a system that uses an M-bit operating system (OS) kernel to support N-bit user processes. During operation, the system receives an exception. Note...
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7451300 |
Explicit control of speculation
Described are methods and systems that allow partial speculation (e.g., speculation within constraints). With partial speculation, after a fault is detected for example, speculation remains enabled...
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7447732 |
Recoverable return code tracking and notification for autonomic systems
A system, method and article of manufacture return code management in autonomic systems and more particularly to managing execution of operations in data processing systems on the basis of return...
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7444500 |
Method for executing a 32-bit flat address program during a system management mode interrupt
A method and system for executing 32-bit flat address programs during a System Management Interrupt. The system provides a 16-bit SMI routine that is given control when an SMI occurs. That routine...
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7437542 |
Identifying and processing essential and non-essential code separately
A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate...
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7434035 |
Method and system for processing instructions in grouped and non-grouped modes
An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor...
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7434039 |
Computer processor capable of responding with comparable efficiency to both software-state-independent and state-dependent events
A technique for enabling a computer processor to be capable of responding with comparable efficiency to both: (i) events whose handling is independent on the state of the software machine that...
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7434038 |
Microprocessor arrangement for updating flag bits for security purposes and method for operating the same
Microprocessor arrangement and a method for operating a microprocessor arrangement, where the microprocessor arrangement has an execution unit for controlling a program cycle and for processing...
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7426630 |
Arbitration of window swap operations
In one embodiment, a processor comprises a register file, register management logic coupled to the register file, and at least two sources of window swap operations coupled to the register...
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7418584 |
Executing system management mode code as virtual machine guest
In one embodiment, a register in a processor is programmable with an intercept indication indicative of whether or not an event that would cause a transition by the processor to a first mode is to...
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7418585 |
Symmetric multiprocessor operating system for execution on non-independent lightweight thread contexts
A multiprocessing system is disclosed. The system includes a multithreading microprocessor including a plurality of thread contexts (TCs), each having a program counter and a general purpose...
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7401211 |
Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor
In a multi-threaded processor, a long latency data dependent thread is flushed from the execution pipelines. Once the stalled thread is flushed, the non-stalling threads in the pipeline can...
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7398372 |
Fusing load and alu operations
Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a...
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7398378 |
Allocating lower priority interrupt for processing to slave processor via master processor currently processing higher priority interrupt through special interrupt among processors
In a multi-processor system with a master-slave configuration, interrupts are efficiently allocated and processed between the processors to improve a real-time performance. A master processor (MP)...
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7398371 |
Shared translation look-aside buffer and method
A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an...
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7389496 |
Condition management system and a method of operation thereof
For use with a processor employing a hierarchical register consolidation structure (HRCS), a condition management system and method of operation thereof. In one embodiment, the system includes a...
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7389407 |
Central control system and method for using state information to model inflight pipelined instructions
A method and apparatus to control logic sections of a pipeline instruction processor is disclosed. A state machine is provided that models the flow of instructions through the pipeline. The state...
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7386647 |
System and method for processing an interrupt in a processor supporting multithread execution
A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to...
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7386710 |
Methods and apparatus for scalable array processor interrupt detection and response
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution...
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