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7617388 Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution  
An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at...
7581089 Method of protecting a computer stack  
A method of protecting a return address on a computer stack is disclosed. Two stacks are created, the first a normal stack, and the second, or shadow, having shadow frames containing the return...
7526638 Hardware alteration of instructions in a microcode routine  
Processor logic gates are used to modify microcode instructions, while they are being executed. The results of previous operations are used by the hardware to modify subsequent instructions in a...
7478228 Apparatus for generating return address predictions for implicit and explicit subroutine calls  
An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address and...
7472259 Multi-cycle instructions  
In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall...
7444501 Methods and apparatus for recognizing a subroutine call  
An apparatus for recognizing a subroutine call is disclosed. The apparatus includes a circuit comprising a first input for receiving contents of a register, a second input for receiving a...
7412593 Processor for processing a program with commands including a mother program and a sub-program  
A processor for processing a program with commands, which has a mother program with a sub-program jump command and a sub-program, which is to be processed in response to the sub-program jump...
7401210 Selecting subroutine return mechanisms  
Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect a...
7386709 Controlling execution of a block of program instructions within a computer processing system  
A data processing apparatus is provided with an execute block instruction EMB which specifies a memory location of a block of program instructions to be executed as well as the length of that block...
7383425 Massively reduced instruction set processor  
This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry to...
7343482 Program subgraph identification  
There is provided an apparatus for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program...
7237098 Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence  
A microprocessor for predicting a target address of a return instruction is disclosed. The microprocessor includes a BTAC and a return stack that each makes a prediction of the target address....
7219218 Vector technique for addressing helper instruction groups associated with complex instructions  
The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply,...
7216220 Microprocessor with customer code store  
A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not...
7203827 Link and fall-through address formation using a program counter portion selected by a specific branch address bit  
A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address...
7203826 Method and apparatus for managing a return stack  
A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels...
7162621 Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration  
An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at...
7130942 Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding  
A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor...
7103759 Microcontroller architecture supporting microcode-implemented peripheral devices  
Methods and apparatus for creating microcode-implemented peripheral devices for a microcontroller core formed in a monolithic integrated circuit. The microcontroller core has a control store for...
6973563 Microprocessor including return prediction unit configured to determine whether a stored return address corresponds to more than one call instruction  
Various embodiments of methods and systems for implementing a return address prediction mechanism in a microprocessor are disclosed. In one embodiment, a return address prediction mechanism...
6970966 System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol  
A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, or FPGA, or similar silicon devices includes a main module connected to the...
6948005 Peripheral device for programmable controller  
A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands specifying...
6910124 Apparatus and method for recovering a link stack from mis-speculation  
A method of performing link stack operations comprises the steps of reading and writing to a link stack. During a write, a location in the link stack pointed to by a current write pointer is...
6898699 Return address stack including speculative return address buffer with back pointers  
An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative...
6898698 Device predicting a branch of an instruction equivalent to a subroutine return and a method thereof  
A register number of a link register, which is specified by an instruction equivalent to a subroutine call, is registered. The number of a branch destination register in a branch instruction which...
6874081 Selection of link and fall-through address using a bit in a branch address for the selection  
A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address...
6813707 Enhancing instruction execution using built-in macros  
An instruction execution system using an “on-chip” ROM device to store one or more frequently used MACROs. A MACRO CALL instruction is used to redirect an instruction stream to one or more...
6772324 Processor having multiple program counters and trace buffers outside an execution pipeline  
In one embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least...
6718414 Function modification in a write-protected operating system  
An apparatus and method are disclosed for runtime modification of called functions within a write-protected operating system. The access state of a processor is altered to allow modification of the...
6711672 Method and system for implementing subroutine calls and returns in binary translation sub-systems of computers  
A sequence of input language (IL) instructions of a guest system is converted, for example by binary translation, into a corresponding sequence of output language (OL) instructions of a host...
6711641 Operation processing apparatus  
The operation processing apparatus comprises a trap selecting register which stores trap maps for selecting one operating system in which the operation processing apparatus is applied out of a...
6697938 Microcomputer executing an ordinary branch instruction and a special branch instruction  
A microcomputer has a built-in memory and is accessible to an external memory. The microcomputer executes a specific area branch instruction “JM” as an executable instruction. The specific area...
6671664 Management of uncommitted register values during random program generation  
A method and an apparatus make available uncommitted register values during the random code generation process. When there is a need for a register to contain a specific (desirable) value, then the...
6609191 Method and apparatus for speculative microinstruction pairing  
An apparatus and method are provided for speculatively pairing micro instructions for parallel execution within a single pipeline of a microprocessor and subsequently splitting the paired micro...
6598151 Stack Pointer Management  
A processor ( 100 ) is provided that is a programmable digital signal processor (DSP) with variable instruction length. A user stack region ( 910 ) is used to pass variables to a subroutine and to...
6530017 System and method providing an arrangement for efficiently emulating an operating system call  
An operating system call control subsystem is disclosed for use in a computer that includes a processor for processing a program, the program instructions of an operating system call instruction...
6526503 Apparatus and method for accessing a memory device during speculative instruction branching  
Instruction branching circuitry including a plurality of logical stacks each having a plurality of entries for storing an address for accessing a corresponding instruction in a memory device. A...
6522934 Dynamic unit selection in a process control system  
A process control system includes a controller that executes a control routine which performs a series of unit procedures within a process. The control routine is written or created to specify the...
6519696 Paired register exchange using renaming register map  
An apparatus and method are provided for performing a floating point exchange operation in a pipeline microprocessor in zero effective clock cycles. The present invention exploits the pattern of...
6446196 Method apparatus and computer program product including one-of and one-of-and-jump instructions for processing data communications  
A method, apparatus and computer program product are provided including one-of and one-of-and-jump instructions for use with processing data communications in a communications system. A one-of...
6349384 System, apparatus and method for processing instructions  
A data processing system comprises means for identifying and replacing instructions to jump to functions having known prolog instructions with modified jump instructions, means for storing the...
6338136 Pairing of load-ALU-store with conditional branch  
An apparatus and method are provided for executing a compare-and-jump operation in a pipeline microprocessor. Typically, the compare-and-jump operation is specified by two micro instructions. The...
6289446 Exception handling utilizing call instruction with context information  
In-code context data used for exception handling is incorporated into a special call instruction which is recognized by the processor. The information is skipped at the time of the function call...
6253315 Return address predictor that uses branch instructions to track a last valid return address  
A processor pipeline includes a return stack buffer (RSB) and a top of stack pointer (RSB_TOS) to indicate the status of buffer entries. A copy of the current RSB_TOS (C_TOS) is associated with...
6212630 Microprocessor for overlapping stack frame allocation with saving of subroutine data into stack area  
When a subroutine call instruction is transferred from the instruction memory 39 to the IDB 29 and decoded by the decoder 18, the following operations (1)-(3) are executed in parallel: (1) a return...
6205539 Method for manipulating a stack pointer with post increment/decrement operation  
A method is provided for controlling a stack memory with a stack pointer. The method is composed of four major steps in a four phase instruction cycle. The first phase of the method decodes an...
6170054 Method and apparatus for predicting target addresses for return from subroutine instructions utilizing a return address cache  
A method of operation in a microprocessor is provided. A return address cache (RAC) is initialized. The RAC includes a portion to store predicted subroutine return addresses (PSRA) and first and...
6154865 Instruction processing pattern generator controlling an integrated circuit tester  
A pattern generator for an integrated circuit tester includes an instruction memory storing addressable instructions (INST) and reading out each instruction when addressed by an address (ADDR)...
6094726 Digital signal processor using a reconfigurable array of macrocells  
A real time digital systolic processor with a core of reconfigurable interconnected macrocells which can be programmed according to function for processing high bandwidth digital data. Each...
6070220 Jump code generator, interrupt program selection system, interruption program selection method, and computer with the function  
An interrupt program selection system which is provided with a central processing unit executing various types of control programs stored in a storage unit and which accepts an interrupt processing...
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