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8990546 Data processing system with safe call and return  
Embodiments of a system and method are disclosed that can include a memory unit, and a memory management unit coupled to the memory unit. The memory management unit can include address mapping...
8959317 Processor and method for saving designated registers in interrupt processing based on an interrupt factor  
A microcomputer includes: a plurality of register lists having a plurality of register patterns, respectively, wherein each of plurality of register patterns designates registers, data of which...
8943300 Method and apparatus for generating return address predictions for implicit and explicit subroutine calls using predecode information  
An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address...
8694760 Branch prediction using a leading value of a call stack storing function arguments  
A branch prediction mechanism within an information processing device comprises a call stack where function arguments are stacked when function calls are performed. The call stack stores arguments...
8555041 Method for performing a return operation in parallel with setting status flags based on a return value register test  
Various embodiments include methods and related media for performing operations including a return operation. One such method includes testing a content of a return value register and setting...
8438371 Link stack repair of erroneous speculative update  
Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively...
8438372 Link stack repair of erroneous speculative update  
Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively...
8423968 Template-based vertical microcode instruction trace generation  
Method, system and computer program product for template-based vertical microcode instruction trace generation. An exemplary embodiment includes an instruction trace generation method, including...
8296750 Optimization of a target program  
A method and apparatus for optimizing a target program including a pattern of instructions to be replaced. The method is performed by execution of program code by a processor of an information...
8250349 Branch prediction control device having return address stack and method of branch prediction  
A branch prediction control device, in an information processing unit which performs a pipeline process, generates a branch prediction address used for verification of an instruction being...
8087018 Managing and supporting multithreaded resources for native code in a heterogeneous managed runtime environment  
A computer implemented method and apparatus to manage multithread resources in a multiple instruction set architectures environment comprising initializing a first thread from a first context. The...
7971044 Link stack repair of erroneous speculative update  
Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively...
7900027 Scalable link stack control method with full support for speculative operations  
A computer implemented method, a processor chip, a computer program product, and a data processing system managing a link stack. The data processing system utilizes speculative pushes onto and...
7882338 Method, system and computer program product for an implicit predicted return from a predicted subroutine  
A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer...
7836290 Return address stack recovery in a speculative execution computing apparatus  
A technique recovers return address stack (RAS) content and restores alignment of a RAS top-of-stack (TOS) pointer for occurrences of mispredictions due to speculative operation, out-of-order...
7831660 System and method for contents upload using a mobile terminal  
The present invention relates to a network system providing a wireless website and method for providing and connecting the wireless website using the same, the network system including a contents...
7793086 Link stack misprediction resolution  
A method for link stack misprediction resolution using a rename structure for tracking the link stack processing, in order to quickly resolve link stack corruption from mispredicted function...
7685404 Program subgraph identification  
An apparatus is provided for processing data under control of a program having program instructions and subgraph suggestion information identifying respective sequences of program instructions...
7647489 Function calling mechanism with embedded index for a handler program and an embedded immediate value for passing a parameter  
A data processing system 2 is provided which includes an instruction decoder 18 responsive to a handler branch instruction HLB, HBLP which includes an index value field to calculate a handler...
7617388 Virtual instruction expansion using parameter selector defining logic operation on parameters for template opcode substitution  
An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at...
7581089 Method of protecting a computer stack  
A method of protecting a return address on a computer stack is disclosed. Two stacks are created, the first a normal stack, and the second, or shadow, having shadow frames containing the return...
7526638 Hardware alteration of instructions in a microcode routine  
Processor logic gates are used to modify microcode instructions, while they are being executed. The results of previous operations are used by the hardware to modify subsequent instructions in a...
7478228 Apparatus for generating return address predictions for implicit and explicit subroutine calls  
An apparatus for emulating the branch prediction behavior of an explicit subroutine call is disclosed. The apparatus includes a first input which is configured to receive an instruction address...
7472259 Multi-cycle instructions  
In one embodiment, a pipelined processor is described that includes an execution pipeline having a plurality of stages and a multi-cycle instruction (MCI) controller adapted to assert a stall...
7444501 Methods and apparatus for recognizing a subroutine call  
An apparatus for recognizing a subroutine call is disclosed. The apparatus includes a circuit comprising a first input for receiving contents of a register, a second input for receiving a...
7412593 Processor for processing a program with commands including a mother program and a sub-program  
A processor for processing a program with commands, which has a mother program with a sub-program jump command and a sub-program, which is to be processed in response to the sub-program jump...
7401210 Selecting subroutine return mechanisms  
Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect...
7386709 Controlling execution of a block of program instructions within a computer processing system  
A data processing apparatus is provided with an execute block instruction EMB which specifies a memory location of a block of program instructions to be executed as well as the length of that...
7383425 Massively reduced instruction set processor  
This invention is directed to a method and apparatus for providing low, predictable latencies in processing IP packets. The apparatus provides a specialized microprocessor or hardwired circuitry...
7219218 Vector technique for addressing helper instruction groups associated with complex instructions  
The present application describes a method and a system for executing instructions while reducing the logic required for execution in a processor. Instructions (e.g., atomic, integer-multiply,...
7216220 Microprocessor with customer code store  
A microprocessor including memory storage into which ISA customer code routines can be stored after having been decoded into their machine-native microinstructions. The customer code store is not...
7203827 Link and fall-through address formation using a program counter portion selected by a specific branch address bit  
A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address...
7203826 Method and apparatus for managing a return stack  
A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels...
7162621 Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration  
An extendable instruction set architecture is provided. In an embodiment, a microprocessor includes a memory, a virtual instruction expansion store, and substitution logic. The memory stores at...
7130942 Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding  
A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the...
7103759 Microcontroller architecture supporting microcode-implemented peripheral devices  
Methods and apparatus for creating microcode-implemented peripheral devices for a microcontroller core formed in a monolithic integrated circuit. The microcontroller core has a control store for...
6973563 Microprocessor including return prediction unit configured to determine whether a stored return address corresponds to more than one call instruction  
Various embodiments of methods and systems for implementing a return address prediction mechanism in a microprocessor are disclosed. In one embodiment, a return address prediction mechanism...
6970966 System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol  
A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, or FPGA, or similar silicon devices includes a main module connected to the...
6948005 Peripheral device for programmable controller  
A storage unit stores ranges of devices allocated for each sequence program. A device range checking unit sequentially extracts device notations indicating consecutive areas and commands...
6910124 Apparatus and method for recovering a link stack from mis-speculation  
A method of performing link stack operations comprises the steps of reading and writing to a link stack. During a write, a location in the link stack pointed to by a current write pointer is...
6898699 Return address stack including speculative return address buffer with back pointers  
An apparatus for storing predicted return addresses of instructions being executed by a pipelined processor, the apparatus includes a two part return address buffer that includes a speculative...
6898698 Device predicting a branch of an instruction equivalent to a subroutine return and a method thereof  
A register number of a link register, which is specified by an instruction equivalent to a subroutine call, is registered. The number of a branch destination register in a branch instruction which...
6874081 Selection of link and fall-through address using a bit in a branch address for the selection  
A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address...
6813707 Enhancing instruction execution using built-in macros  
An instruction execution system using an “on-chip” ROM device to store one or more frequently used MACROs. A MACRO CALL instruction is used to redirect an instruction stream to one or more MACROs...
6772324 Processor having multiple program counters and trace buffers outside an execution pipeline  
In one embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least...
6718414 Function modification in a write-protected operating system  
An apparatus and method are disclosed for runtime modification of called functions within a write-protected operating system. The access state of a processor is altered to allow modification of...
6711672 Method and system for implementing subroutine calls and returns in binary translation sub-systems of computers  
A sequence of input language (IL) instructions of a guest system is converted, for example by binary translation, into a corresponding sequence of output language (OL) instructions of a host...
6711641 Operation processing apparatus  
The operation processing apparatus comprises a trap selecting register which stores trap maps for selecting one operating system in which the operation processing apparatus is applied out of a...
6697938 Microcomputer executing an ordinary branch instruction and a special branch instruction  
A microcomputer has a built-in memory and is accessible to an external memory. The microcomputer executes a specific area branch instruction “JM” as an executable instruction. The specific area...
6671664 Management of uncommitted register values during random program generation  
A method and an apparatus make available uncommitted register values during the random code generation process. When there is a need for a register to contain a specific (desirable) value, then...

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