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7624258 Using computation histories to make predictions  
Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not...
7613910 Information processing apparatus, method, and computer-readable recording medium for replacing an entry in a memory device  
The present invention relates to an information processing apparatus predicting a branch destination of a branch instruction using a branch history register to realize effective replacement by...
7590830 Method and structure for concurrent branch prediction in a processor  
Concurrently branch predicting for multiple branch-type instructions demands of high performance environments. Concurrently branch predicting for multiple branch-type instructions provides the...
7577827 Data processor with multi-command instruction words  
A data processor that addresses instructions as groups of commands which may contain more than one branch command, such as VLIW instructions that contain several commands for parallel execution....
7565512 Method, system and apparatus for generation of global branch history  
Systems, methods and apparatuses for the generation of a global history are disclosed. Embodiments of the present invention may provide logic operable to generate a global history and a global...
7552314 Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address  
The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is...
7533252 Overriding a static prediction with a level-two predictor  
In one embodiment, the present invention includes a method for determining if an entry corresponding to a prediction address is present in a first predictor, and overriding a prediction output from...
7523298 Polymorphic branch predictor and method with selectable mode of prediction  
A polymorphic branch predictor and method includes a plurality of branch prediction methods. The methods are selectively enabled to perform branch prediction. A selection mechanism is configured to...
7519777 Methods, systems and computer program products for concomitant pair prefetching  
Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride...
7500088 Methods and apparatus for updating of a branch history table  
Methods and apparatus are provided for enhanced instruction handling in processing environments. If branch misprediction occurs during instruction processing, a branch history table may be updated...
7493480 Method and apparatus for prefetching branch history information  
A two level branch history table (TLBHT) is substantially improved by providing a mechanism to prefetch entries from the very large second level branch history table (L2 BHT) into the active (very...
7493447 System and method for caching sequential programs  
Methods and related computer program products, systems, and devices for using a NAND flash as a program ROM are disclosed.
7487340 Local and global branch prediction information storage  
Embodiments of the invention provide a method of storing branch prediction information. In one embodiment, the method includes receiving a branch instruction and storing local branch prediction...
7484042 Data processing system and method for predictively selecting a scope of a prefetch operation  
A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains,...
7472264 Predicting a jump target based on a program counter and state information for a process  
One embodiment of the present invention provides a system that predicts a jump target for a jump instruction. During operation, the system starts fetching the jump instruction while executing a...
7461243 Deferred branch history update scheme  
In one embodiment, a processor comprises a branch prediction array, an index generator coupled to the branch prediction array, and a control unit coupled to the index generator. The branch...
7454602 Pipeline having bifurcated global branch history buffer for indexing branch history table per instruction fetch group  
A method and apparatus for updating global branch history information are disclosed. A dynamic branch predictor within a data processing system includes a global branch history (GBH) buffer and a...
7454597 Computer processing system employing an instruction schedule cache  
A processor core and method of executing instructions, both of which utilizes schedules, are presented. Each of the schedules includes a sequence of instructions, an address of a first of the...
7447885 Reading prediction outcomes within a branch prediction mechanism  
A branch prediction mechanism includes a history value register storing a history value which is used to address into a history buffer from which a plurality of prediction values are read and...
7437543 Reducing the fetch time of target instructions of a predicted taken branch instruction  
A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may...
7430657 System, method and device for queuing branch predictions  
A system, method and device for storing branch predictions in a queue that may be connected to a branch prediction unit, and for delivering the stored predictions to an instruction fetch unit. A...
7428632 Branch prediction mechanism using a branch cache memory and an extended pattern cache  
A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a...
7428627 Method and apparatus for predicting values in a processor having a plurality of prediction modes  
A multi-mode predictor for a processor having a plurality of prediction modes is disclosed. The prediction modes are used to predict non-binary values. The predictor is a multi-mode predictor...
7426631 Methods and systems for storing branch information in an address table of a processor  
Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit...
7426628 Run-time node prefetch prediction in dataflow graphs  
A method for run-time prediction of a next caller of a shared functional unit, wherein the shared functional unit is operable to be called by two or more callers out of a plurality of callers. The...
7418583 Data dependency detection using history table of entry number hashed from memory address  
A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least...
7409535 Branch target prediction for multi-target branches by identifying a repeated pattern  
An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of...
7380110 Branch prediction structure with branch direction entries that share branch prediction qualifier entries  
An efficient branch prediction structure is described that bifurcates a branch prediction structure into at least two portions where information stored in the second portion is aliased amongst...
7370183 Branch predictor comprising a split branch history shift register  
An apparatus and a system, as well as a method and article, may operate to predict a branch within a first operating context, such as a user context, using a first strategy; and to predict a branch...
7350062 Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal  
An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a...
7337271 Context look ahead storage structures  
A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing...
7320066 Branch predicting apparatus and branch predicting method  
A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack...
7293164 Autonomic method and apparatus for counting branch instructions to generate branch statistics meant to improve branch predictions  
A method, apparatus, and computer instructions for autonomically counting selected branch instructions executed in a processor to improve branch predictions. Counters are provided to count branch...
7290255 Autonomic method and apparatus for local program code reorganization using branch count per instruction hardware  
A method, apparatus, and computer instructions for local program reorganization using branch count per instruction hardware. In a preferred embodiment, a hardware counter is used in the present...
7278012 Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions  
A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and...
7266676 Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays  
Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the...
7237098 Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence  
A microprocessor for predicting a target address of a return instruction is disclosed. The microprocessor includes a BTAC and a return stack that each makes a prediction of the target address....
7234046 Branch prediction using precedent instruction address of relative offset determined based on branch type and enabling skipping  
A method of predicting and skipping branch instructions for pipelines which need more than one cycle to predict branch direction and branch target addresses in microprocessors and digital signal...
7197630 Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation  
A method and system for changing the executable status of an operation following a branch misprediction. In one embodiment, a method may include predicting an execution path of a first conditional...
7174444 Preventing a read of a next sequential chunk in branch prediction of a subject chunk  
A system and method of early branch prediction in a processor to evaluate, typically before a full branch prediction is made, ways in a branch target buffer to determine if any of said ways...
7165169 Speculative branch target address cache with selective override by secondary predictor based on branch instruction type  
A branch prediction apparatus having a primary predictor and a secondary predictor that selectively overrides the primary predictor based on the type of branch instruction decoded. A branch target...
7165168 Microprocessor with branch target address cache update queue  
A microprocessor with a write queue for a branch target address cache (BTAC) is disclosed. The BTAC is read in parallel with an instruction cache in order to predict a target address of a branch...
7162619 Apparatus and method for densely packing a branch instruction predicted by a branch target address cache and associated target instructions into a byte-wide instruction buffer  
A branch control apparatus in a microprocessor. A register receives a first cache line containing a branch instruction from an instruction cache in response to a fetch address. The fetch address...
7159102 Branch control memory  
A branch control memory store branch instructions which are adapted for optimizing performance of programs run on electronic processors. Flexible instruction parameter fields permit a variety of...
7143273 Method and apparatus for dynamic branch prediction utilizing multiple stew algorithms for indexing a global history  
Toggling between accessing an entry in a global history with a stew created from branch predictions implied by the ordering of instructions within a trace of a trace cache when a trace is read out...
7143272 Using computation histories to make predictions  
Associated with an instruction in a program is a computation history. The computation history represents all objects that affect the result of the instruction, such objects including (but not...
7139903 Conflict free parallel read access to a bank interleaved branch predictor in a processor  
A computer system has a processor that has a prediction array that avoids conflicts when the prediction array is accessed twice in once clock cycle to retrieve predictions for two separate...
7136992 Method and apparatus for a stew-based loop predictor  
A method and apparatus for a loop predictor for predicting the end of a loop is disclosed. In one embodiment, the loop predictor may have a predict counter to hold a predict count representing the...
7134005 Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte  
A microprocessor caches in a branch target address cache (BTAC), for each of a plurality of previously executed branch instructions: a prediction of whether the branch instruction will be taken and...
7120784 Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment  
Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better...
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