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8145888 |
Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit
A data processing circuit has an execution circuit (18) with a plurality of functional units (20). An instruction decoder (17) is operable in a first and a second instruction mode. In the first...
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8127115 |
Group formation with multiple taken branches per group
Disclosed are a method and a system for grouping processor instructions for execution by a processor, where the group of processor instructions includes at least two branch processor instructions....
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8117423 |
Pipeline replay support for multicycle operations
Instructions asserted in the instruction pipeline (3) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (15)...
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8117357 |
System core for transferring data between an external device and memory
Details of a highly cost effective and efficient implementation of a manifold array (ManArray) architecture and instruction syntax for use therewith are described herein. Various aspects of this...
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8108658 |
Data processing circuit wherein functional units share read ports
A data processing circuit comprises a register file (14) having read ports and write ports. A plurality of functional units (21a-c), is coupled to receive operand data from a same combination of...
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8095775 |
Instruction pointers in very long instruction words
During operation of a VLIW processor, a very long instruction word is fetched. A portion of the very long instruction word that includes a pointer to an instruction is identified, and the...
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8069335 |
Processing system and method for executing instructions
A processing system for executing instructions comprises a first part (11) having address information and a plurality of data bits, E0 to EN. According to one embodiment, each data bit E0 to EN...
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8046568 |
Microprocessor with integrated high speed memory
The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and...
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8019971 |
Processor for executing highly efficient VLIW
A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation...
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8015391 |
Simultaneous multiple thread processor increasing number of instructions issued for thread detected to be processing loop
A processor simultaneously issues instructions to multiple threads in a same instruction execution cycle. An instruction issuer controls issuance of an instruction for each of the multiple threads....
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7971197 |
Automatic instruction set architecture generation
A digital computer system automatically creates an Instruction Set Architecture (ISA) that potentially exploits VLIW instructions, vector operations, fused operations, and specialized operations...
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7962719 |
Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with...
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7895413 |
Microprocessor including register renaming unit for renaming target registers in an instruction with physical registers in a register sub-file
A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions,...
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7886135 |
Pipeline replay support for unaligned memory operations
Instructions asserted in a microprocessors instruction pipeline (3) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (5) that is...
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7873794 |
Mechanism that provides efficient multi-word load atomicity
Disclosed is an apparatus, method, and program product that provides atomic, multi-word load support without incurring additional memory utilization. A double-word is atomically loaded without the...
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7861061 |
Processor instruction including option bits encoding which instructions of an instruction packet to execute
A processor and a method for executing VLIW instructions by first fetching a VLIW instruction and then identifying from option bits encoded in a first one of the instructions within the fetched...
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7831804 |
Multidimensional processor architecture
A processor architecture includes a number of processing elements for treating input signals. The architecture is organized according to a matrix including rows and columns, the columns of which...
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RE41703 |
Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication
A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory...
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7774581 |
Apparatus for compressing instruction word for parallel processing VLIW computer and method for the same
An apparatus and a method are provided for a parallel processing very long instruction word (VLIW) computer. The apparatus includes: an index code generation unit sequentially generating an index...
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7747843 |
Microprocessor with integrated high speed memory
A computer system with a processor architecture having more than one execution channel is described. The processor architecture contains at least one load/store unit for loading and storing data...
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7739479 |
Method for providing physics simulation data
A method of providing physics data within a game program or simulation using a hardware-based physics processing unit having unique architecture designed to efficiently calculate physics related data.
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7694301 |
Method and system for supporting input/output for a virtual machine
A method for supporting input/output for a virtual machine. The method includes the step of executing virtual machine application instructions, wherein the application instructions are executed...
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7685403 |
Pipeline replay support for multi-cycle operations
Instructions asserted in the instruction pipeline (3) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline (15)...
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7681046 |
System with secure cryptographic capabilities using a hardware specific digital secret
A system with secure cryptographic capabilities using a hardware specific digital secret.
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7673119 |
VLIW optional fetch packet header extends instruction set space
This invention is useful in a very long instruction word data processor that fetches a predetermined plural number of instructions each operation cycle. A predetermined one of these instructions is...
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7669041 |
Instruction-parallel processor with zero-performance-overhead operand copy
A processor having a zero-overhead operand copy capability. The processor includes multiple execution units to execute instructions in parallel and multiple register files each associated with one...
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7664929 |
Data processing apparatus with parallel operating functional units
A program of instruction words is executed with a VLIW data processing apparatus. The apparatus comprises a plurality of functional units capable of executing a plurality of instructions from each...
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7647474 |
Saving system context in the event of power loss
Embodiments of a method and system for saving system context after a power outage are disclosed herein. A power agent operates to reduce the possibility of data corruption due to partially written...
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7647473 |
Instruction processing method for verifying basic instruction arrangement in VLIW instruction for variable length VLIW processor
An instruction processing method for checking an arrangement of basic instructions in a very long instruction word (VLIW) instruction, suitable for language processing systems, an assembler and a...
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7627735 |
Implementing vector memory operations
In one embodiment, the present invention includes an apparatus having a register file to store vector data, an address generator coupled to the register file to generate addresses for a vector...
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RE41012 |
Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor
A double indirect method of accessing a block of data in a register file is used to allow efficient implementations without the use of specialized vector processing hardware. In addition, the...
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7590824 |
Mixed superscalar and VLIW instruction issuing and processing method and system
Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal...
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7584405 |
Fault-detecting computer system
A method for detecting computational errors in a digital processor executing a program. Initially, the program is divided into computation segments, and source code for at least one of the segments...
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7574583 |
Processing apparatus including dedicated issue slot for loading immediate value, and processing method therefor
Differences in encoding efficiency of instructions may arise if certain operations require very large immediate values as operands, as opposed to others requiring no immediate values or small...
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7533244 |
Network-on-chip dataflow architecture
Network-on-Chip Dataflow Architecture is the new microprocessor architecture. It consists of many processing elements connecting together via two distinct networks namely instruction network and...
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7533243 |
Processor for executing highly efficient VLIW
A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation...
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7506137 |
Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions
Techniques for adding more complex instructions and their attendant multi-cycle execution units with a single instruction multiple data stream (SIMD) very long instruction word (VLIW) processing...
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7496656 |
Processing instruction words
A method for processing an instruction word in a data processing system, the instruction word comprising a plurality of instruction bit positions, each bit position corresponding to an instruction...
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7484075 |
Method and apparatus for providing fast remote register access in a clustered VLIW processor using partitioned register files
Effective remote register file access time can be reduced in a clustered VLIW processor using partitioned register files and some additional hardware for pre-fetching remote registers. An...
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7475222 |
Multi-threaded processor having compound instruction and operation formats
A processor comprises a memory, an instruction decoder coupled to the memory for decoding instructions retrieved therefrom, and a plurality of execution units for executing the decoded...
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7472257 |
Rerouting VLIW instructions to accommodate execution units deactivated upon detection by dispatch units of dedicated instruction alerting multiple successive removed NOPs
Processor (100) has a plurality of registers (120) for storing instructions for execution by the plurality of execution units (160). The plurality of registers (120) are coupled to the plurality of...
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7444276 |
Hardware acceleration system for logic simulation using shift register as local cache
A logic simulation processor stores in a shift register intermediate values generated during the logic simulation. The simulation processor includes multiple processor units and an interconnect...
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7437534 |
Local and global register partitioning technique
A Very Long Instruction Word (VLIW) processor having a plurality of functional units includes a multi-ported register file that is divided into a plurality of separate register file segments, each...
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7424594 |
Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecture
Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with...
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7418575 |
Long instruction word processing with instruction extensions
A system for adding reconfigurable computational instructions to a computer, the system comprising a processor operable to execute a set of instructions of a computer program comprising a set of...
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7412591 |
Apparatus and method for switchable conditional execution in a VLIW processor
An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoder loads and...
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7409530 |
Method and apparatus for compressing VLIW instruction and sharing subinstructions
A VLIW instruction format is introduced having a set of control bits which identify subinstruction sharing conditions. At compilation the VLIW instruction is analyzed to identify subinstruction...
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7401204 |
Parallel Processor efficiently executing variable instruction word
A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information....
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7398372 |
Fusing load and alu operations
Fusing a load micro-operation (uop) together with an arithmetic uop. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a...
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7395408 |
Parallel execution processor and instruction assigning making use of group number in processing elements
The parallel execution processor 100 fetches a piece of instruction data. When the piece of instruction data includes only one instruction, the instruction decoding unit 120 assigns the one...
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