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8181005 |
Hybrid branch prediction device with sparse and dense prediction caches
A system and method for branch prediction in a microprocessor. A hybrid device stores branch prediction information in a sparse cache for no more than a common smaller number of branches within...
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8171269 |
Branch target buffer with entry source field for use in determining replacement priority
Various embodiments of the present invention provide systems and methods for branch prediction. As an example, some embodiments of the present invention provides processor circuits that include a...
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8171260 |
Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address
The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is...
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8166279 |
Method for predictive decoding of a load tagged pointer instruction
Predictive decoding is achieved by fetching an instruction, accessing a predictor containing predictor information including prior instruction execution characteristics, obtaining predictor...
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8151096 |
Method to improve branch prediction latency
An apparatus to generate a branch prediction of an instruction based at least in part on the address of the previous branch instruction, wherein the previous instruction is prior to the instruction...
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8140833 |
Implementing polymorphic branch history table reconfiguration
A method, apparatus and computer program product are provided for implementing polymorphic branch history table (BHT) reconfiguration. A BHT includes a plurality of predetermined configurations...
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8131976 |
Tracking effective addresses in an out-of-order processor
Mechanisms, in a data processing system, are provided for tracking effective addresses through a processor pipeline of the data processing system. The mechanisms comprise logic for fetching an...
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8127119 |
Control-flow prediction using multiple independent predictors
The present disclosure generally describes computing systems with a multi-core processor comprising one or more branch predictor arrangements. The branch predictor are configured to predict a...
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8099721 |
Parsing of declarations in all branches of preprocessor conditionals
Declarations from an input source code or tokenized source code are serialized into a stream of tokens produced by following each branch of a preprocessor conditional directive statement that...
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8099586 |
Branch misprediction recovery mechanism for microprocessors
A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition...
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8086831 |
Indexed table circuit having reduced aliasing
In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of...
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8082428 |
Methods and system for resolving simultaneous predicted branch instructions
A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions,...
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8078852 |
Predictors with adaptive prediction threshold
An adaptive prediction threshold scheme for dynamically adjusting prediction thresholds of entries in a Pattern History Table (PHT) by observing global tendencies of the branch or branches that...
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8078850 |
Branch prediction technique using instruction for resetting result table pointer
Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch...
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8042179 |
False code execution prevention method, program for the method, and recording medium for recording the program
A method for preventing a return address from being falsified due to a buffer overflow during the program execution, and for detecting the buffer-overflow beforehand. When the return address is...
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8041931 |
Branch prediction apparatus, systems, and methods
An apparatus and a system, as well as a method and article, may operate to predict a branch within a first operating context, such as a user context, using a first strategy; and to predict a branch...
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8037288 |
Hybrid branch predictor having negative ovedrride signals
Various embodiments are described relating to processors, branch predictors, branch prediction systems, and computing systems.
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8028180 |
Method and system for power conservation in a hierarchical branch predictor
A method and system for power conservation in a hierarchical branch predictor system are provided. The method includes addressing multiple branch predictors, each of the branch predictors having...
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8019376 |
Method and system for loop data distribution general field of invention and state of the art
A method for loop distribution of a plurality of data blocks corresponding to objects fragments, or aggregates of objects such as alphanumeric messages, screen pages, graphic objects integrated in...
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8006070 |
Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling system
An information handling system includes a processor that throttles an instruction fetcher whenever a group of instructions in a branch instruction queue together exhibits a confidence in the...
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8001363 |
System for speculative branch prediction optimization and method thereof
A value representative of a processor's speculative branch prediction efficiency is determined and the speculative branch prediction depth is adjusted accordingly. The processor's speculative...
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7996618 |
Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional...
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7984280 |
Storing branch information in an address table of a processor
Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an...
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7984279 |
System and method for using a working global history register
A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline...
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7979725 |
Computer power conservation apparatus and method that controls speculative execution by adjusting branch confidence threshold based on processor load
A computer measures a processor load and configures itself so that a lesser amount of speculative execution is enabled when the processor is lightly loaded than is enabled when the processor is...
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7975133 |
Method for repairing a speculative global history record
A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor...
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7966479 |
Concurrent vs. low power branch prediction
An instruction processing circuit includes a decoder circuit, a basic block builder circuit, a multi-block builder circuit, first and second predictor circuits, and a sequencer circuit, where the...
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RE42466 |
Branch predicting apparatus and branch predicting method
A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack...
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7962722 |
Branch target address cache with hashed indices
In at least one embodiment, a processor includes at least one execution unit that executes instructions and instruction sequencing logic, coupled to the at least one execution unit, that fetches...
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7962733 |
Branch prediction mechanisms using multiple hash functions
In one embodiment, the branch prediction mechanism includes a first storage including a first plurality of locations for storing a first set of partial prediction information. The branch prediction...
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7949862 |
Branch prediction table storing addresses with compressed high order bits
Address control section includes an encoding section to generate higher-order address information made by compressing a predetermined higher-order bit part from predetermined higher-order and...
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7949861 |
Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline
In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such...
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7945767 |
Recovery apparatus for solving branch mis-prediction and method and central processing unit thereof
A recovery apparatus for solving a branch mis-prediction, and a method and a central processing unit (CPU) thereof are provided. The recovery apparatus includes an instruction buffer, at least one...
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7940277 |
Processor for executing extract controlled by a register instruction
A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of...
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7941654 |
Local and global branch prediction information storage
Embodiments of the invention provide an apparatus of storing branch prediction information. In one embodiment, an integrated circuit device includes a first table for storing local branch...
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7934081 |
Apparatus and method for using branch prediction heuristics for determination of trace formation readiness
A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional...
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7925870 |
Return target address prediction by moving entry pointer to return stack popped at completion to deeper one at return instruction fetch
An instruction fetch control apparatus includes an instruction completion notifier, and an entry designation unit predicting a return address of a subroutine during an instruction fetching. The...
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7925868 |
Suppressing register renaming for conditional instructions predicted as not executed
Within a data processing system including a register renaming mechanism, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional...
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7925871 |
Identification and correction of cyclically recurring errors in one or more branch predictors
A data processing apparatus 2 is provided with one or more branch predictors 10 for generating branch predictions. A supervising predictor 12 is responsive to at least a stream of branch...
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7913068 |
System and method for providing asynchronous dynamic millicode entry prediction
A system and method for asynchronous dynamic millicode entry prediction in a processor are provided. The system includes a branch target buffer (BTB) to hold branch information. The branch...
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7904705 |
System and method for repairing a speculative global history record
A system and method are provided for updating a speculative global history prediction record in a microprocessor system using pipelined instruction processing. The method accepts microprocessor...
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7900026 |
Target branch prediction using a plurality of tables
A system for predicting multiple targets for a single branch includes: a branch target buffer that includes a previous next address for an instruction and that receives an indirect instruction...
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7900019 |
Data access target predictions in a data processing system
A data processing apparatus having a plurality of memories is provided in which address generation logic (109) outputs to at least one of the plurality of memories a target memory address...
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7895422 |
Selective postponement of branch target buffer (BTB) allocation
A system and method provides branch target buffer (BTB) allocation. When a branch instruction is received, a branch target address that corresponds to the branch instruction is determined. A...
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7890738 |
Method and logical apparatus for managing processing system resource use for speculative execution
A method and logical apparatus for managing processing system resource use for speculative execution reduces the power and performance burden associated with inefficient speculative execution of...
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7890739 |
Method and apparatus for recovering from branch misprediction
Embodiments of the present invention provide a system that executes a branch instruction. When executing the branch instruction, the system obtains a stored prediction of a resolution of the branch...
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7886134 |
Loop iteration prediction by supplying pseudo branch instruction for execution at first iteration and storing history information in branch prediction unit
This invention combines a loop support mechanism and a branch prediction mechanism. After an instruction execution unit executes an end block instruction of a block repeat, the loop control unit...
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7882337 |
Method and system for efficient tentative tracing of software in multiprocessors
A method of tentative tracing execution events in a multiprocessor system. Each processor stores tentative events in a corresponding buffer. The processor sets pointers in an array to a head and...
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7877578 |
Processing apparatus for storing branch history information in predecode instruction cache
The present invention provides an information processing apparatus having a predecoder decoding an operation code in an input instruction, generating conditional branch instruction information...
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7873819 |
Branch target buffer addressing in a data processor
A branch target buffer (BTB) receives, from a processor, a current fetch group address which corresponds to a current fetch group including a plurality of instructions. In response to the current...
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