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7624254 |
Segmented pipeline flushing for mispredicted branches
A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed...
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7617387 |
Methods and system for resolving simultaneous predicted branch instructions
A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions,...
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7613910 |
Information processing apparatus, method, and computer-readable recording medium for replacing an entry in a memory device
The present invention relates to an information processing apparatus predicting a branch destination of a branch instruction using a branch history register to realize effective replacement by...
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7610474 |
Mechanism for hardware tracking of return address after tail call elimination of return-type instruction
A technique maintains return address stack (RAS) content and alignment of a RAS top-of-stack (TOS) pointer upon detection of a tail-call elimination of a return-type instruction. In at least one...
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7600102 |
Condition bits for controlling branch processing
A processing pipeline with a plurality of pipeline stages is described, with the processing pipeline comprising a front end and a back end. The processing pipeline's front end comprises an array...
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7590830 |
Method and structure for concurrent branch prediction in a processor
Concurrently branch predicting for multiple branch-type instructions demands of high performance environments. Concurrently branch predicting for multiple branch-type instructions provides the...
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7577827 |
Data processor with multi-command instruction words
A data processor that addresses instructions as groups of commands which may contain more than one branch command, such as VLIW instructions that contain several commands for parallel execution....
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7552314 |
Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address
The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is...
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7533252 |
Overriding a static prediction with a level-two predictor
In one embodiment, the present invention includes a method for determining if an entry corresponding to a prediction address is present in a first predictor, and overriding a prediction output from...
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7529914 |
Method and apparatus for speculative execution of uncontended lock instructions
A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will...
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7526760 |
Methods for implementing virtual method invocation with shared code
A method for implementing virtual method invocation when a compiled code of an invoked method is shared between class types that share a runtime representation is provided. In this method, an entry...
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7523298 |
Polymorphic branch predictor and method with selectable mode of prediction
A polymorphic branch predictor and method includes a plurality of branch prediction methods. The methods are selectively enabled to perform branch prediction. A selection mechanism is configured to...
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7519798 |
Utilizing a branch predictor outcome to decide whether to fetch or not to fetch from a branch target buffer
A method, system and branch predictor for branch prediction. The system includes a processor core for executing instructions, a branch target buffer for fetching a branch address, and a branch...
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7519777 |
Methods, systems and computer program products for concomitant pair prefetching
Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride...
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7516313 |
Predicting contention in a processor
In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction,...
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7509472 |
Collapsible front-end translation for instruction fetch
Address translation for instruction fetching can be obviated for sequences of instruction instances that reside on a same page. Obviating address translation reduces power consumption and increases...
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7496916 |
Service and recovery using multi-flow redundant request processing
Methods, systems and articles of manufacture for performing multiple request processing. Redundant instances of executing entities service requests in a time-delayed fashion, relative to one...
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7493607 |
Statically speculative compilation and execution
A system, for use with a compiler architecture framework, includes performing a statically speculative compilation process to extract and use speculative static information, encoding the...
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7493447 |
System and method for caching sequential programs
Methods and related computer program products, systems, and devices for using a NAND flash as a program ROM are disclosed.
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7490229 |
Storing results of resolvable branches during speculative execution to predict branches during non-speculative execution
One embodiment of the present invention provides a system that facilitates storing results of resolvable branches during speculative execution, and then using the results to predict the same...
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7487340 |
Local and global branch prediction information storage
Embodiments of the invention provide a method of storing branch prediction information. In one embodiment, the method includes receiving a branch instruction and storing local branch prediction...
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7487334 |
Branch encoding before instruction cache write
Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes...
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7484042 |
Data processing system and method for predictively selecting a scope of a prefetch operation
A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains,...
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7472264 |
Predicting a jump target based on a program counter and state information for a process
One embodiment of the present invention provides a system that predicts a jump target for a jump instruction. During operation, the system starts fetching the jump instruction while executing a...
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7472263 |
Method and apparatus for prediction handling multiple branches simultaneously
A branch prediction apparatus includes a branch information receiving unit that receives simultaneously, branch information for each of a plurality of branch instructions that are completed...
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7461243 |
Deferred branch history update scheme
In one embodiment, a processor comprises a branch prediction array, an index generator coupled to the branch prediction array, and a control unit coupled to the index generator. The branch...
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7461211 |
System, apparatus and method for generating nonsequential predictions to access a memory
A system, apparatus, and method are disclosed for storing and prioritizing predictions to anticipate nonsequential accesses to a memory. In one embodiment, an exemplary apparatus is configured as a...
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7454602 |
Pipeline having bifurcated global branch history buffer for indexing branch history table per instruction fetch group
A method and apparatus for updating global branch history information are disclosed. A dynamic branch predictor within a data processing system includes a global branch history (GBH) buffer and a...
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7454596 |
Method and apparatus for partitioned pipelined fetching of multiple execution threads
Methods and apparatus for partitioning a microprocessor pipeline to support pipelined branch prediction and instruction fetching of multiple execution threads. A thread selection stage selects a...
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7447885 |
Reading prediction outcomes within a branch prediction mechanism
A branch prediction mechanism includes a history value register storing a history value which is used to address into a history buffer from which a plurality of prediction values are read and...
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7447884 |
Multi-table branch prediction circuit for predicting a branch's target address based on the branch's delay slot instruction address
A first storage unit stores an address of a branching instruction and a branched address. A first detector detects whether or not an instruction of the present address has previously been branched...
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7447881 |
Branch prediction apparatus and method
A branch prediction apparatus has a configuration such that a predicted branch target address and an offset are obtained by referring to a branch history, an instruction fetch address and the...
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7428632 |
Branch prediction mechanism using a branch cache memory and an extended pattern cache
A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a...
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7426631 |
Methods and systems for storing branch information in an address table of a processor
Methods and systems for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit...
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7424578 |
Computer system, compiler apparatus, and operating system
A compiler apparatus for a computer system capable of improving the hit rate of a cache memory, which includes a prefetch target extraction device, a thread activation process insertion device, and...
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7421572 |
Branch instruction for processor with branching dependent on a specified bit in a register
A processor such as a parallel hardware-based multithreaded processor ( 12 ) is described. The processor ( 12 ) can execute a computer instruction that is a branch instruction that causes an...
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7404070 |
Branch prediction combining static and dynamic prediction techniques
A computer system comprises a processor that comprises a hardware branch predictor and software instructions executed by the processor. The software instructions comprise conditional branch...
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7380111 |
Out-of-order processing with predicate prediction and validation with correct RMW partial write new predicate register values
A method for processing registers in an out-of-order processor. A predicate in an instruction is predicted. An architecturally correct value is then computed using a read-modify-write operation....
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7380110 |
Branch prediction structure with branch direction entries that share branch prediction qualifier entries
An efficient branch prediction structure is described that bifurcates a branch prediction structure into at least two portions where information stored in the second portion is aliased amongst...
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7346737 |
Cache system having branch target address cache
A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The...
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7343481 |
Branch prediction in a data processing system utilizing a cache of previous static predictions
A data processing system incorporates an instruction prefetch unit 8 including a static branch predictor 12 . A static branch prediction cache 30, 32, 34 is provided for storing a most...
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7337271 |
Context look ahead storage structures
A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing...
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7334143 |
Computer power conservation apparatus and method that enables less speculative execution during light processor load based on a branch confidence threshold value
A computer measures a processor load and configures itself so that a lesser amount of speculative execution is enabled when the processor is lightly loaded than is enabled when the processor is...
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7334115 |
Detection, recovery and prevention of bogus branches
The present invention provides for a method and apparatus for the detection and prevention of and recovery from bogus branch predictions in a microprocessor. Micro-ops, decoded from a macro...
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7320066 |
Branch predicting apparatus and branch predicting method
A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack...
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7302556 |
Method, apparatus and computer program product for implementing level bias function for branch prediction control for generating test simulation vectors
A method, apparatus and computer program product are provided for implementing a level bias function for branch prediction control for generating test simulation vectors. User selected options are...
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7302380 |
Simulation apparatus, method and program
A simulation apparatus for simulating a pipeline processor including a pipeline simulation unit and an instruction simulation unit. The simulation apparatus includes a pipeline simulation unit is...
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7293265 |
Methods and apparatus to perform return-address prediction
Methods and apparatus to perform return-address prediction in a program are described herein. In an example method, a procedure associated with an overflow condition is detected. A branch-hint...
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7293164 |
Autonomic method and apparatus for counting branch instructions to generate branch statistics meant to improve branch predictions
A method, apparatus, and computer instructions for autonomically counting selected branch instructions executed in a processor to improve branch predictions. Counters are provided to count branch...
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7266676 |
Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays
Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the...
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