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5797012 Connectivity based program partitioning  
A method for partitioning programs into multi-procedure modules for efficient compilation. During interprocedural analysis, a weighted callgraph of the program is constructed in which weights on...
5794027 Method and apparatus for managing the execution of instructons with proximate successive branches in a cache-based data processing system  
A small buffer called a branch-anticipate buffer (BAB) is used to store groups of instructions which are likely to be required from the instruction cache (I-cache) when an instruction prefetch miss...
5784603 Fast handling of branch delay slots on mispredicted branches  
An apparatus and method for quickly and efficiently handling mispredicted branch instructions in a computer processor having multiple instruction execution pipelines and utilizing branch delay slot...
5771377 System for speculatively executing instructions using multiple commit condition code storages with instructions selecting a particular storage  
A processing device executes an instruction speculatively, and execution result of the instruction becomes valid when all the predictions about true/false of branch condition are correct, and the...
5768576 Method and apparatus for predicting and handling resolving return from subroutine instructions in a computer processor  
A method and apparatus for resolving Return From Subroutine instructions in a computer processor are disclosed. The method and apparatus resolve Return From Subroutine instructions in four stages....
5764946 Superscalar microprocessor employing a way prediction unit to predict the way of an instruction fetch address and to concurrently provide a branch prediction address corresponding to the fetch address  
A superscalar microprocessor is provided employing a way prediction unit which predicts the next fetch address as well as the way of the instruction cache that the current fetch address hits in...
5765208 Method of speculatively executing store instructions prior to performing snoop operations  
A data processor (10) has a load/store unit (28) that executes store-to-shared-data instructions before it exclusively owns the data designated by the instruction. Later, a bus interface unit (12)...
5761490 Changing the meaning of a pre-decode bit in a cache memory depending on branch prediction mode  
A system for changing the meaning of a pre-decode branch field associated with an instruction in an instruction cache memory of a computer system compatible with multiple branch prediction modes....
5761723 Data processor with branch prediction and method of operation  
A data processor (10) has a branch target address cache (48) for storing the target addresses of a number of recently taken branch instructions. Normally, each fetch address is compared to the...
5758142 Trainable apparatus for predicting instruction outcomes in pipelined processors  
A predictor which chooses between two or more predictors is described. The predictor includes a first component predictor which operates according to a first algorithm to produce a prediction of an...
RE35794 System for reducing delay for execution subsequent to correctly predicted branch instruction using fetch information stored with each block of instructions in cache  
A super-scaler processor is disclosed wherein branch-prediction information is provided within an instruction cache memory. Each instruction cache block stored in the instruction cache memory...
5742803 Method of performing a compilation process for determining a branch probability and an apparatus for performing the compilation process  
When a flow graph is created for a program including a complex if statement, the respective branch conditions in the complex if statement are separated and the flow graph designating the control...
5742805 Method and apparatus for a single history register based branch predictor in a superscalar microprocessor  
Methods and apparati predict whether conditional branch computer instructions should be taken or not taken. A history register is maintained to record the history of groups of instructions, updated...
5740418 Pipelined processor carrying out branch prediction by BTB  
A pipelined processor includes a main memory, an instruction cache, a BTB, and a BTB registration discriminator for decoding instructions line fetched from the main memory at the time of mishit of...
5740393 Instruction pointer limits in processor that performs speculative out-of-order instruction execution  
A method for enforcing an instruction pointer limit in a processor, wherein a retire circuit determines a speculative instruction pointer for a set of retiring instruction during a retirement...
5740417 Pipelined processor operating in different power mode based on branch prediction state of branch history bit encoded as taken weakly not taken and strongly not taken states  
A low-power pipelined data processor (20) includes a branch prediction mechanism for speculatively placing branch target instructions into the fetch, decode, dispatch, and execute pipeline when a...
5737590 Branch prediction system using limited branch target buffer updates  
In a BTB, a lower part (ten-odd bits) of a branch target address obtained when a branch target generator executes a branch instruction is entered or updated as a prediction index. A linker links a...
5734881 Detecting short branches in a prefetch buffer using target location information in a branch target cache  
A pipelined x86 processor includes a prefetch unit (prefetch buffer) and a branch unit that cooperate to detect when the target of a branch (designated a short branch) is already in the prefetch...
5721893 Exploiting untagged branch prediction cache by relocating branches  
An untagged branch prediction cache is exploited by relocating branches during a final pass in the compilation process, after all other optimizations have been applied, where a pass is made over...
5706491 Branch processing unit with a return stack including repair using pointers from different pipe stages  
A branch processing unit (BPU) is used, in an exemplary embodiment, in a superscalar, superpipelined microprocessor compatible with the x86 instruction set architecture. The BPU includes a return...
5692167 Method for verifying the correct processing of pipelined instructions including branch instructions and self-modifying code in a microprocessor  
An apparatus and method for improving the performance of pipelined computer processors which have segment bits for specifying the operand size, the address size for memory reference, and the stack...
5669010 Cascaded two-stage computational SIMD engine having multi-port memory and multiple arithmetic units  
A two-stage cascaded processor engine for Digital Signal Processing (DSP) utilizing parallel multi-port memories and a plurality of arithmetic units, including adders and multiplier-accumulators...
5659752 System and method for improving branch prediction in compiled program code  
A method and system for optimizing branch prediction in an executable computer program compiled for execution on a pipelined processor that employs branch prediction. The source program is compiled...
5655115 Processor structure and method for watchpoint of plural simultaneous unresolved branch evaluation  
Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based...
5655122 Optimizing compiler with static prediction of branch probability, branch frequency and function frequency  
A compiler and method for optimizing a program based on branch probabilities, branch frequencies and function frequencies. A number of algorithms executed by the compiler determine statically from...
5642500 Method and apparatus for controlling instruction in pipeline processor  
A pipeline processor for processing instruction fetch prior to execution of the instruction based on the content of branch history for storing history of the result of execution of branch...
5634119 Computer processing unit employing a separate millicode branch history table  
A computer processing system includes a first memory that stores instructions belonging to a first instruction set architecture and a second memory that stores instructions belonging to a second...
5625837 Processor architecture having out-of-order execution, speculative branching, and giving priority to instructions which affect a condition code  
A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic...
5608886 Block-based branch prediction using a target finder array storing target sub-addresses  
A target finder array in the instruction cache contains a lower portion of the target address and a block encoding indicating if the target address is within the same 2K-byte block that the branch...
5606676 Branch prediction and resolution apparatus for a superscalar computer processor  
An apparatus and method for improving the performance of superscalar pipelined computers using branch prediction and verification that the predicted branch is correct. A predicted branch may be...
5596735 Circuit and method for addressing segment descriptor tables  
In a processor having a protected mode of operation in which a computer memory associated with the processor contains global and local descriptor tables addressed by a combination of a base address...
5592636 Processor architecture supporting multiple speculative branches and trap handling  
A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic...
5592634 Zero-cycle multi-state branch cache prediction data processing system and method thereof  
A branch cache (40) has a plurality of storage levels (120, 122, 140, and/or 142) wherein at least two write registers (114 and 116) are used to perform a parallel write operation to at least two...
5586278 Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor  
A method of state recovery following a branch misprediction or an undetected branch instruction. If, during execution of a branch instruction in an out-of-order unit, it is determined that the...
5526498 Pipeline processor, with a return address stack and two stack pointers, for storing pre-return processed addresses  
A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a...
5524224 System for speculatively executing instructions wherein mispredicted instruction is executed prior to completion of branch processing  
A processing system and method of operation are provided, In response to a branch instruction, a first instruction is processed so that a storage location is associated with the first instruction...
5515518 Two-level branch prediction cache  
AN improved branch prediction cache (BPC) scheme that utilizes a hybrid cache structure. The BPC provides two levels of branch information caching. The fully associative first level BPC is a...
5469551 Method and apparatus for eliminating branches using conditional move instructions  
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The...
5454089 Branch look ahead adder for use in an instruction pipeline sequencer with multiple instruction decoding  
Logic examines signals from an instruction fetch unit to determine if the next instruction is a branch. A mux selects one of the 4 instruction words. MACRO [0:3] and a displacement from the...
5440704 Data processor having branch predicting function  
An instruction loaded in an instruction register is decoded by an instruction decoder and the branch predicting bit which indicates whether the instruction is branched or not is read out from a...
5355457 Data processor for performing simultaneous instruction retirement and backtracking  
A data processing system is provided which has more general purpose physical registers than architectural (logical) registers. The data processing system uses a register inventory system to monitor...
5321820 Processor for executing a conditional branch instruction at a high speed by pre-reading a result flag  
A processor which is provided with an execution portion having an n-stage pipeline for performing an operation on input data and for outputting the result of the operation and a result flag...
5317703 Information processing apparatus using an advanced pipeline control method  
An information processing method and apparatus for applying pipeline control and an advanced control to a sequence of instructions to be executed. The instruction sequence contains a plurality of...
5295248 Branch control circuit  
A branch prediction control circuit has a register. A main memory provides a machine language instruction to the register and an instruction buffer. The prediction control circuit decodes the...
5283873 Next line prediction apparatus for a pipelined computed system  
A next line prediction mechanism for predicting a next instruction index to an instruction cache of a computer pipeline, has a latency equal to the cycle time of the instruction cache to maximize...
5276825 Apparatus for quickly determining actual jump addresses by assuming each instruction of a plurality of fetched instructions is a jump instruction  
A method and apparatus for performing a fast jump address calculation is disclosed. A field from the instruction is provided to an adder, on the assumption that it is the displacement value,...
5237664 Pipeline circuit  
A pipeline circuit adopted for a CPU or a microprocessor in a computer system, computes the effective branch destination address of a conditional branch instruction before or in parallel with the...
5201057 System for extracting low level concurrency from serial instruction streams  
An architecture for a central processing unit (cpu) provides for the extraction of low-level concurrency from sequential instruction streams. The cpu includes an instruction queue, a plurality of...
5193156 Data processor with pipeline which disables exception processing for non-taken branches  
The data processor of this invention is provided with a multi-stage pipeline processing mechanism which predicts the probability of the branch instruction branching at the instruction decoding...
5179673 Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline  
A method and arrangement for producing a predicted subroutine return address in response to entry of a subroutine return instruction in a computer pipeline that has a ring pointer counter and a...
Matches 351 - 400 out of 415 < 1 2 3 4 5 6 7 8 9 >