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5964868 Method and apparatus for implementing a speculative return stack buffer  
A return stack buffer mechanism that uses two separate return stack buffers is disclosed. The first return stack buffer is the Speculative Return Stack Buffer. The Speculative Return Stack Buffer...
5964870 Method and apparatus for using function context to improve branch  
An apparatus for predicting branch behavior during execution of branch instructions in a computer program. The apparatus comprises a branch table buffer (BTB) to store a plurality of branch...
5954814 System for using a branch prediction unit to achieve serialization by forcing a branch misprediction to flush a pipeline  
A microprocessor includes an instruction fetch unit, a branch prediction unit, and a decode unit. The instruction fetch unit is adapted to retrieve a plurality of program instructions. The program...
5954815 Invalidating instructions in fetched instruction blocks upon predicted two-step branch operations with second operation relative target address  
A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch...
5954816 Branch selector prediction  
A branch prediction unit includes a branch prediction entry corresponding to a group of contiguous instruction bytes. The branch prediction entry stores branch predictions corresponding to branch...
5949995 Programmable branch prediction system and method for inserting prediction operation which is independent of execution of program code  
A system for predicting branches in a computer system is provided having a memory containing program code comprising a plurality of instructions, said instructions including branch instructions and...
5948106 System for thermal overload detection and prevention for an integrated circuit processor  
A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is...
5948100 Branch prediction and fetch mechanism for variable length instruction, superscalar pipelined processor  
A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion....
5944817 Method and apparatus for implementing a set-associative branch target buffer  
A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target...
5946468 Reorder buffer having an improved future file for storing speculative instruction execution results  
A reorder buffer for a microprocessor comprising a control unit, an instruction storage, and future file. The future file has storage locations associated with each register implemented in the...
5943494 Method and system for processing multiple branch instructions that write to count and link registers  
A system and method for processing count and link branch instructions that allows multiple branches to be outstanding at the same time without being limited to the number of rename registers...
5935238 Selection from multiple fetch addresses generated concurrently including predicted and actual target by control-flow instructions in current and previous instruction bundles  
A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit farther is capable of handling multiple...
5935241 Multiple global pattern history tables for branch prediction in a microprocessor  
A microprocessor (10) and a system (300) incorporating the same is disclosed, in which branch prediction is effected in response to the type of program in which branching instructions are...
5931944 Branch instruction handling in a self-timed marking system  
An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling...
5930821 Method and apparatus for shared cache lines in split data/code caches  
An apparatus and method for sharing cache lines within a split data/code cache is provided. The invention utilizes cache snoop and state control, coupled to both a data cache and a code cache,...
5928358 Information processing apparatus which accurately predicts whether a branch is taken for a conditional branch instruction, using small-scale hardware  
A branch instruction includes a set of branch prediction information 13b and a set of branch history information 13c. The set of branch prediction information 13b is made up of 1 bit which predicts...
5926634 Limited run branch prediction  
A branch prediction technique which increases the likelihood of correctly predicting the direction of a conditional branch instruction is presented. The technique is based on the observation that...
5918046 Method and apparatus for a branch instruction pointer table  
A buffer is used to store information about the branch instructions within a pipelined microprocessor that can speculatively execute instructions. When a branch instruction in the microprocessor is...
5915110 Branch misprediction recovery in a reorder buffer having a future file  
A reorder buffer for a microprocessor comprising a control unit, an instruction storage, and future file. The future file has storage locations associated with each register implemented in the...
5898865 Apparatus and method for predicting an end of loop for string instructions  
A superscalar microprocessor implements a microcode instruction unit that predicts the end of microcode loops. The microcode instruction unit detects a microcode loop and begins counting the number...
5896529 Branch prediction based on correlation between sets of bunches of branch instructions  
A method for a prediction correlation between a first group of branch instructions in a bunch of instructions and a second group of branch instructions in a bunch of instructions is disclosed. The...
5896528 Superscalar processor with multiple register windows and speculative return address generation  
A superscaler processor capable of executing multiple instructions concurrently. The processor includes a program counter which identifies instructions for execution by multiple execution units....
5887159 Dynamically determining instruction hint fields  
A computer implemented method for dynamically setting hint fields of instructions. Machine executable code is modified during execution to locate and replace instructions having hint fields. The...
5881277 Pipelined microprocessor with branch misprediction cache circuits, systems and methods  
A microprocessor comprising an instruction pipeline (36) comprising a plurality of successive instruction stages. An instruction passes from a beginning stage (38), through a plurality of...
5870599 Computer system employing streaming buffer for instruction preetching  
Streaming buffer renaming for memory accesses issued by a microprocessor to an external memory via a system bus allows up to N fetch accesses at any one time for M physical streaming buffer...
5870575 Indirect unconditional branches in data processing system emulation mode  
A processor and method of operating a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, a series of...
5867682 High performance superscalar microprocessor including a circuit for converting CISC instructions to RISC operations  
A superscalar microprocessor is provided which includes a integer functional unit and a floating point functional unit that share a high performance main data processing bus. The integer unit and...
5867699 Instruction flow control for an instruction processor  
Method and apparatus for changing the sequential execution of instructions in a pipelined instruction processor by using a microcode controlled redirect controller. The execution of a redirect...
5860152 Method and apparatus for rapid computation of target addresses for relative control transfer instructions  
A method and apparatus accepts a relative control transfer instruction and generates a compact absolute control transfer instruction which may have a number of bits one greater than the relative...
5857104 Synthetic dynamic branch prediction  
A compiler includes a branch statistics data analyzer to analyze branch statistics data of a branch instruction to construct a branch predictor function for the branch instruction. A branch...
5850542 Microprocessor instruction hedge-fetching in a multiprediction branch environment  
An apparatus for fetching instructions in a computer system is disclosed. The apparatus includes a cache circuit for holding a sub-set of main store, a buffer circuit for holding instructions...
5848269 Branch predicting mechanism for enhancing accuracy in branch prediction by reference to data  
A branch predicting apparatus includes a prediction information buffer for supplying prediction information related to branch prediction of a branch instruction, at a same timing as fetching of an...
5848268 Data processor with branch target address generating unit  
A data processor, comprising: an instruction fetch unit 111 which fetches instructions from a memory which stores instructions; an instruction decoding unit 112 which decodes the instructions...
5842008 Method and apparatus for implementing a branch target buffer cache with multiple BTB banks  
A Branch Target Buffer Circuit in a computer processor that predicts branch instructions within a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target...
5838962 Interrupt driven dynamic adjustment of branch predictions  
Branch predictions are adjusted by interrupting a central processing unit and observing a pending branch instruction. An interrupt is generated using a counter, timer, or software-based interrupt....
5835754 Branch prediction system for superscalar processor  
Each entry of BTBs (11 and 21) stores branch prediction information on a branch instruction including a 2-bit offset which indicates a location at which the branch instruction is stored in a cache...
5832260 Processor microarchitecture for efficient processing of instructions in a program including a conditional program flow control instruction  
A processor microarchitecture for efficient processing of instructions in a program including a program flow control instruction. The program flow control instruction specifies a target instruction...
5826074 Extenstion of 32-bit architecture for 64-bit addressing with shared super-page register  
A processor has 64-bit operand execution pipelines, but a 32-bit branch pipeline. The branch pipeline contains registers to hold the lower 32-bit sub-addresses of 64-bit target and sequential...
5822575 Branch prediction storage for storing branch prediction information such that a corresponding tag may be routed with the branch instruction  
A prediction storage for branch predictions and information corresponding to branch instructions which are outstanding within an instruction processing pipeline of a microprocessor. A branch tag is...
5822574 Functional unit with a pointer for mispredicted resolution, and a superscalar microprocessor employing the same  
A superscalar microprocessor is provided having functional units which receive a pointer (a reorder buffer tag) which is compared to the reorder buffer tags of the instructions currently being...
5822576 Branch history table with branch pattern field  
The detection and selection of the appropriate branch target address in a branch history table in super scalar microprocessor is simplified by reducing the complexity of the branch history table...
5819079 Instruction fetch on demand for uncacheable memory which avoids memory mapped I/O side effects in a processor with speculative instruction fetch  
A computer system includes an instruction prefetching mechanism that detects whether an instruction to be prefetched is located in a region of memory that is uncacheable. To perform an instruction...
5819080 Microprocessor using an instruction field to specify condition flags for use with branch instructions and a computer system employing the microprocessor  
A microprocessor is provided including a branch prediction unit configured to select one of multiple sets of condition flags for use by a branch instruction according to the segment register...
5812839 Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit  
A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch...
5812838 Branch history table  
In a branch processing unit a branch history table is accessed by a branch instruction address associated with a scanned branch instruction before the entire address has been computed. The branch...
5809294 Parallel processing unit which processes branch instructions without decreased performance when a branch is taken  
A parallel processing unit operable in a delayed branch method has a branch-delay slot filled with instructions to be executed when a branch by a branch instruction is taken. The instructions in...
5809324 Multiple instruction dispatch system for pipelined microprocessor without branch breaks  
A microprocessor with a dispatch unit which dispatches a maximum number of instructions each cycle, without splitting into separate blocks after a branch instruction. A mispredicted branch is...
5805878 Method and apparatus for generating branch predictions for multiple branch instructions indexed by a single instruction pointer  
A method and apparatus for generating respective branch predictions for first and second branch instructions, both indexed by a first instruction pointer, is disclosed. The apparatus includes...
5805877 Data processor with branch target address cache and method of operation  
A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. A branch unit (20) generates a fetch address that depends upon a condition...
5799167 Instruction nullification system and method for a processor that executes instructions out of order  
An instruction nullification system facilitates handling of nullification dependencies in a processor that executes instructions out of order. Instructions are forwarded from an instruction fetch...
Matches 301 - 350 out of 417 < 1 2 3 4 5 6 7 8 9 >