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6195744 Unified multi-function operation scheduler for out-of-order execution in a superscaler processor  
A superscalar processor includes a scheduler which selects operations for out-of-order execution. The scheduler contains storage and control logic which is partitioned into entries corresponding to...
6185676 Method and apparatus for performing early branch prediction in a microprocessor  
A pipelined microprocessor having a branch prediction unit implemented in an instruction pointer generation stage of the microprocessor. The branch prediction unit includes a memory device having...
6182211 Conditional branch control method  
In order to effectively reduce branch hazards without a restriction to a structure of a pipeline, the contents of instructions and the like during control of conditional branching in an information...
6178498 Storing predicted branch target address in different storage according to importance hint in branch prediction instruction  
A branch prediction instruction is provided that includes hint information for indicating a storage location for associated branch prediction information in a hierarchy of branch prediction storage...
6175896 Microprocessor system and method for increasing memory Bandwidth for data transfers between a cache and main memory utilizing data compression  
A microprocessor includes a cache memory, a bus interface unit, and an execution engine. The bus interface unit is connected to the cache memory and adapted to receive compressed data from a main...
6167506 Replacing displacement in control transfer instruction with encoding indicative of target address, including offset and target cache line location  
The processor is configured to predecode instruction bytes prior to their storage within an instruction cache. During the predecoding, relative branch instructions are detected. The displacement...
6167509 Branch performance in high speed processor  
A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The...
6167510 Instruction cache configured to provide instructions to a microprocessor having a clock cycle time less than a cache access time of said instruction cache  
An apparatus including a banked instruction cache and a branch prediction unit is provided. The banked instruction cache allows multiple instruction fetch addresses (comprising consecutive...
6157986 Fast linear tag validation unit for use in microprocessor  
A linearly addressed cache capable of fast linear tag validation after a context switch or a translation lookaside buffer (TLB) flush. The cache is configured to validate multiple linear address...
6157999 Data processing system having a synchronizing link stack and method thereof  
When a request to branch to an address stored in a return memory location (440) occurs, a busy bit is used to determine whether the return memory location (440) contains updated information. When...
6157998 Method for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffers  
A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion...
6151672 Methods and apparatus for reducing interference in a branch history table of a microprocessor  
Interference in a branch history table of a microprocessor is reduced by methods and apparatus which predict the outcome of branch instructions (taken or not taken) through a combination of static...
6134645 Instruction completion logic distributed among execution units for improving completion efficiency  
Each execution unit within a superscalar processor has an associated completion table that contains a copy of the status of all instructions dispatched but not completed. A central completion table...
6134643 Method and apparatus for cache line prediction and prefetching using a prefetch controller and buffer and access history  
A microprocessor includes an execution engine, a prediction table cache, and a prefetch controller. The execution engine is adapted to issue a memory request. The memory request includes an...
6134654 Bi-level branch target prediction scheme with fetch address prediction  
One embodiment of the present invention provides a system for predicting an address of an instruction following a branch instruction in a computer instruction stream. This system concurrently...
6131158 Data processing system capable of executing groups of instructions, including at least one arithmetic instruction, in parallel  
A data processor performs various types of EIT (exception, interrupt, trap) processing in connection with the execution of the preceding and following instructions in parallel. In one embodiment,...
6115809 Compiling strong and weak branching behavior instruction blocks to separate caches for dynamic and static prediction  
A method and apparatus varies branch prediction strategy associated with branch instructions in a trace of program code. The present invention first profiles branch instructions within a trace to...
6115792 Way prediction logic for cache array  
A set-associative cache memory configured to use multiple portions of a requested address in parallel to quickly access data from a data array based upon stored way predictions. The cache memory...
6112300 Method and apparatus for performing multi-way branching using a hardware relational table  
Multi-way branching is implemented via a single instruction by providing a computer system with a hardware token-to-address table, loading the table with branch target data correlating to the...
6101577 Pipelined instruction cache and branch prediction mechanism therefor  
A microprocessor includes an instruction cache having a cache access time greater than the clock cycle time employed by the microprocessor. The instruction cache is banked, and access to alternate...
6092188 Processor and instruction set with predict instructions  
A processor architecture with an instruction set having a predict instruction, the predict instruction providing static prediction information and a statically predicted target address to the...
6088793 Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor  
A microprocessor capable of predicting program branches includes a fetching unit, a branch prediction unit, and a decode unit. The fetching unit is configured to retrieve program instructions,...
6085315 Data processing device with loop pipeline  
The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a...
6081887 System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction  
A technique for predicting the result of a conditional branch instruction for use with a processor having instruction pipeline. A stored predictor is connected to the front end of the pipeline and...
6079006 Stride-based data address prediction structure  
A data prediction structure is provided for a superscalar microprocessor. The data prediction structure stores base addresses and stride values in a prediction array. The base address and the...
6079005 Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address  
A microprocessor employs a branch prediction unit including a branch prediction storage which stores the index portion of branch target addresses and an instruction cache which is virtually indexed...
6079014 Processor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural state  
A processor is disclosed comprising a front end circuit that fetches a series of instructions according to a program sequence determined by at least one branch prediction, a register renaming...
6073230 Instruction fetch unit configured to provide sequential way prediction for sequential instruction fetches  
An instruction fetch unit that employs sequential way prediction. The instruction fetch unit comprises a control unit configured to convey a first index and a first way to an instruction cache in a...
6065100 Caching apparatus and method for enhancing retrieval of data from an optical storage device  
A caching apparatus and method for enhancing retrieval of data from an optical storage device are provided. The apparatus preferably includes a first memory device for storing data therein. The...
6055629 Predicting for all branch instructions in a bunch based on history register updated once for all of any taken branches in a bunch  
A method for a prediction correlation between a first group of branch instructions in a bunch of instructions and a second group of branch instructions in a bunch of instructions is disclosed. The...
6055630 System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units  
An instruction pipeline in a microprocessor is provided. The instruction pipeline includes a plurality of pipeline units, each of the pipeline units processing a plurality of instructions including...
6052776 Branch operation system where instructions are queued until preparations is ascertained to be completed and branch distance is considered as an execution condition  
A method of effecting a branch operation without the need of instruction fetching is carried out according to the taken/untaken branch with respect to a program containing plural branch...
6044459 Branch prediction apparatus having branch target buffer for effectively processing branch instruction  
To provide a branch prediction apparatus and its method that accesses BTB using IP of an instruction whose interval between the branch instruction is the smallest, on the basis of a branch...
6035122 Compiler for converting source program into object program having instruction with commit condition  
A processing device executes an instruction speculatively, and execution result of the instruction becomes valid when all the predictions about true/false of branch condition are correct, and the...
6035392 Computer with optimizing hardware for conditional hedge fetching into cache storage  
A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a...
6035393 Stalling predicted prefetch to memory location identified as uncacheable using dummy stall instruction until branch speculation resolution  
A computer system includes an instruction prefetching mechanism that detects whether an instruction to be prefetched is located in a region of memory that is uncacheable. To perform an instruction...
6035383 Memory access request result prediction prior to confirm signal generation  
A data processing system having a processor core 4, a memory management unit 6 and a cache memory 8 uses the memory management unit 6 to produce a confirm signal C that indicates that a memory...
6029228 Data prefetching of a load target buffer for post-branch instructions based on past prediction accuracy's of branch predictions  
A method of operating a microprocessor (12). The method first receives (64) a plurality of instructions arranged in a sequence from a first instruction through a last instruction. The method second...
6021489 Apparatus and method for sharing a branch prediction unit in a microprocessor implementing a two instruction set architecture  
A microprocessor that includes first and second Instruction Fetch Units (IFU) coupled therebetween is provided. The first IFU implements a first Instruction Set Architecture (ISA). The second IFU...
6018798 Floating point unit using a central window for storing instructions capable of executing multiple instructions in a single clock cycle  
A floating point unit capable of executing multiple instructions in a single clock cycle using a central window and a register map is disclosed. The floating point unit comprises: a plurality of...
6014742 Trace branch prediction unit  
A trace branch prediction unit includes a trace branch target buffer connected to a trace cache. The trace cache stores traces of micro-ops, with the micro-ops being stored non-sequentially. The...
6014741 Apparatus and method for predicting an end of a microcode loop  
A superscalar microprocessor implements a microcode instruction unit that predicts the end of microcode loops. The microcode instruction unit detects a microcode loop and begins counting the number...
6003128 Number of pipeline stages and loop length related counter differential based end-loop prediction  
An apparatus for prediction of loop instructions. Loop instructions decrement the value in a counter register and branch to a target address (specified by an instruction operand) if the decremented...
5987600 Exception handling in a processor that performs speculative out-of-order instruction execution  
A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value...
5987588 Processor architecture providing for speculative execution of instructions with multiple predictive branching and handling of trap conditions  
A processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic...
5978908 Computer instruction supply  
A computer instruction supply system has store and fetch circuitry for obtaining a sequence of instructions, test circuitry for locating the first instruction in the sequence to be enabled, and for...
5978907 Delayed update register for an array  
An update unit for an array in an integrated circuit is provided. The update unit delays the update of the array until a clock cycle in which the functional input to the array is idle. The input...
5974542 Branch prediction unit which approximates a larger number of branch predictions using a smaller number of branch predictions and an alternate target indication  
A branch prediction unit includes a cache-line based branch prediction storage having a branch prediction storage location assigned to each cache line of an instruction cache within the...
5974529 Systems and methods for control flow error detection in reduced instruction set computer processors  
An instruction flow monitoring mechanism performs control flow error detection in a reduced instruction set computer (RISC) processor using signature monitoring. The signature monitoring is...
5968169 Superscalar microprocessor stack structure for judging validity of predicted subroutine return addresses  
A return stack is described which stores return addresses associated with subroutine call instructions along with an ESP register value associated with the subroutine call instructions in a...
Matches 251 - 300 out of 417 < 1 2 3 4 5 6 7 8 9 >