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7577827 Data processor with multi-command instruction words  
A data processor that addresses instructions as groups of commands which may contain more than one branch command, such as VLIW instructions that contain several commands for parallel execution....
7552314 Fetching all or portion of instructions in memory line up to branch instruction based on branch prediction and size indicator stored in branch target buffer indexed by fetch address  
The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is...
7546445 Information processor having delayed branch function with storing delay slot information together with branch history information  
In correspondence with an address of a branch instruction, a branch target address Apb, a valid bit V as branch history information, and delay slot information POS on the last position of delay...
7523298 Polymorphic branch predictor and method with selectable mode of prediction  
A polymorphic branch predictor and method includes a plurality of branch prediction methods. The methods are selectively enabled to perform branch prediction. A selection mechanism is configured to...
7519798 Utilizing a branch predictor outcome to decide whether to fetch or not to fetch from a branch target buffer  
A method, system and branch predictor for branch prediction. The system includes a processor core for executing instructions, a branch target buffer for fetching a branch address, and a branch...
7519777 Methods, systems and computer program products for concomitant pair prefetching  
Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride...
7509472 Collapsible front-end translation for instruction fetch  
Address translation for instruction fetching can be obviated for sequences of instruction instances that reside on a same page. Obviating address translation reduces power consumption and increases...
7493600 Method for verifying branch prediction mechanism and accessible recording medium for storing program thereof  
A method for verifying a branch prediction mechanism and an accessible recording medium for storing a verification program are provided. The method is used for verifying the branch prediction...
7493447 System and method for caching sequential programs  
Methods and related computer program products, systems, and devices for using a NAND flash as a program ROM are disclosed.
7484042 Data processing system and method for predictively selecting a scope of a prefetch operation  
A data processing system includes at least first and second coherency domains each containing at least one processing unit, an interconnect fabric coupling the first and second coherency domains,...
7471574 Branch target buffer and method of use  
A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit...
7447885 Reading prediction outcomes within a branch prediction mechanism  
A branch prediction mechanism includes a history value register storing a history value which is used to address into a history buffer from which a plurality of prediction values are read and...
7447883 Allocation of branch target cache resources in dependence upon program instructions within an instruction queue  
A data processing system includes an instruction fetching circuit 2 , an instruction queue 4 and further processing circuits 6 . A branch target cache, which maybe a branch target address cache...
7447882 Context switching within a data processing system having a branch prediction mechanism  
A branch target buffer is provided which maintains its entries across context switches within a virtually addressed system. Branch mispredictions are detected for individual entries within the...
7447881 Branch prediction apparatus and method  
A branch prediction apparatus has a configuration such that a predicted branch target address and an offset are obtained by referring to a branch history, an instruction fetch address and the...
7437543 Reducing the fetch time of target instructions of a predicted taken branch instruction  
A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may...
7434037 System for target branch prediction using correlation of local target histories including update inhibition for inefficient entries  
An information processing system includes a branch target buffer (BTB) comprising the last next address for the instruction and for receiving an indirect instruction address and providing a BTB...
7409535 Branch target prediction for multi-target branches by identifying a repeated pattern  
An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of...
7398377 Apparatus and method for target address replacement in speculative branch target address cache  
An apparatus and method in a pipelined microprocessor for replacing one of two target addresses in a branch target address cache (BTAC) line. If only one of the two entries is invalid, the invalid...
7350062 Predicted return address from return stack entry designated by computation unit with multiple inputs including return hit flag and re-fetch signal  
An information processing apparatus is capable of speculatively performing an execution, such as a pipeline/superscalar/out-of-order execution and equipped with a branch prediction mechanism (a...
7350037 Digital signal processor and digital signal processing method enabling concurrent program download and execution  
A signal processing device has a program memory for storing program code transferred from an external source under the control of an access control unit having an address counter. The transferred...
7346737 Cache system having branch target address cache  
A cache system has a branch target address cache, including a storage unit for storing branch target address cache (BTAC) access bits each corresponding to cache lines of an instruction cache. The...
7343481 Branch prediction in a data processing system utilizing a cache of previous static predictions  
A data processing system incorporates an instruction prefetch unit 8 including a static branch predictor 12 . A static branch prediction cache 30, 32, 34 is provided for storing a most...
7337271 Context look ahead storage structures  
A memory storage structure includes a memory storage device, and a first meta-structure having a first size and operating at a first speed. The first speed is faster than a second speed for storing...
7328332 Branch prediction and other processor improvements using FIFO for bypassing certain processor pipeline stages  
A processor ( 1700 ) including a pipeline ( 1710, 1740 ) having a fetch pipeline ( 1710 ) with branch prediction circuitry ( 1840 ) to supply respective predicted taken target addresses for branch...
7320066 Branch predicting apparatus and branch predicting method  
A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack...
7266676 Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays  
Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the...
7237098 Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence  
A microprocessor for predicting a target address of a return instruction is disclosed. The microprocessor includes a BTAC and a return stack that each makes a prediction of the target address....
7234025 Microprocessor with repeat prefetch instruction  
A microprocessor that executes a repeat prefetch instruction (REP PREFETCH). The REP PREFETCH prefetches multiple cache lines, wherein the number of cache lines is specifiable in the instruction....
7185186 Apparatus and method for resolving deadlock fetch conditions involving branch target address cache  
An apparatus for avoiding a deadlock condition in a microprocessor with a speculative branch target address cache (BTAC) that predicts a target address of a branch instruction contained in a cache...
7165169 Speculative branch target address cache with selective override by secondary predictor based on branch instruction type  
A branch prediction apparatus having a primary predictor and a secondary predictor that selectively overrides the primary predictor based on the type of branch instruction decoded. A branch target...
7165168 Microprocessor with branch target address cache update queue  
A microprocessor with a write queue for a branch target address cache (BTAC) is disclosed. The BTAC is read in parallel with an instruction cache in order to predict a target address of a branch...
7159102 Branch control memory  
A branch control memory store branch instructions which are adapted for optimizing performance of programs run on electronic processors. Flexible instruction parameter fields permit a variety of...
7152154 Apparatus and method for invalidation of redundant branch target address cache entries  
An apparatus for invalidating redundant entries in an N-way set associative branch target address cache (BTAC) for the same branch instruction is disclosed. An index portion of an instruction cache...
7134124 Thread ending method and device and parallel processor system  
Each processor comprises a register for storing start address of a forked child thread and a comparator for detecting that the value of its own program counter is coincident with the start address...
7134005 Microprocessor that detects erroneous speculative prediction of branch instruction opcode byte  
A microprocessor caches in a branch target address cache (BTAC), for each of a plurality of previously executed branch instructions: a prediction of whether the branch instruction will be taken and...
7124287 Dynamically adaptive associativity of a branch target buffer (BTB)  
Disclosed is a method and apparatus providing the capability to create a dynamic associative branch target buffer (BTB). A dynamically based associative BTB allows for either an increase number of...
7120784 Thread-specific branch prediction by logically splitting branch history tables and predicted target address cache in a simultaneous multithreading processing environment  
Branch prediction logic is enhanced to provide a monitoring function for certain conditions which indicate that the use of separate BHTs and predicted target address cache would provide better...
7117347 Processor including fallback branch prediction mechanism for far jump and far call instructions  
A method and apparatus are provided for processing far jump-call branch instructions within a processor in a manner which reduces the number of stalls of the processor pipeline. The processor...
7107437 Branch target buffer (BTB) including a speculative BTB (SBTB) and an architectural BTB (ABTB)  
A method and apparatus are provided for improving the performance of branch prediction using a combination of a speculative branch target buffer (SBTB) and an architectural branch target buffer...
7096348 Method and apparatus for allocating entries in a branch target buffer  
A method ( 200 ) and apparatus ( 100 ) for allocating entries in a branch target buffer (BTB) ( 144 ) in a pipelined data processing system includes: sequentially fetching instructions; determining...
7093074 Storage control device and storage control method  
A storage control device, and method, the storage control device including storers, such as buffers, which store data and a storage controller. The storage controller, in response to a data issue...
7082520 Branch prediction utilizing both a branch target buffer and a multiple target table  
Improved Branch prediction utilizes both a Branch Target Buffer (BTB) and a Multiple Target Table (MTT) for providing the capability to predict multiple targets for a single branch. A MTT when used...
7062640 Instruction segment filtering scheme  
A filtering system for instruction segments determines whether a new instruction segment satisfies a predetermined filtering condition prior to storage. If the instruction segment fails the...
7047400 Single array banked branch target buffer  
An Instruction Pointer (IP) signal is received comprising an IP tag field and an IP set field. A plurality of entries corresponding to the IP set field are read, each of the entries comprising an...
7039718 Multiprocess computer system  
A multiprocess computer system comprises at least two processes (P 1 , P 2 , . . . Pi, . . . PN) connected by a network. Each process is executed by a piece of hardware equipped with an operating...
6983356 High performance memory device-state aware chipset prefetcher  
A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory...
6970997 PROCESSOR, MULTIPROCESSOR SYSTEM AND METHOD FOR SPECULATIVELY EXECUTING MEMORY OPERATIONS USING MEMORY TARGET ADDRESSES OF THE MEMORY OPERATIONS TO INDEX INTO A SPECULATIVE EXECUTION RESULT HISTORY STORAGE MEANS TO PREDICT THE OUTCOME OF THE MEMORY OPERATION  
When a processor executes a memory operation instruction by means of data dependence speculative execution, a speculative execution result history table which stores history information concerning...
6957327 Block-based branch target buffer  
The invention provides a method and apparatus for branch prediction in a processor. A fetch-block branch target buffer is used in an early stage of pipeline processing before the instruction is...
6920549 Branch history information writing delay using counter to avoid conflict with instruction fetching  
A branch history information write control device in an instruction execution processing apparatus includes a memory unit storing an instruction string, and a branch prediction unit performing a...
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