Matches 1 - 50 out of 121 1 2 3 >
Match Document Document Title
7634644 Effective elimination of delay slot handling from a front section of a processor pipeline  
Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution...
7613907 Embedded software camouflage against code reverse engineering  
Methods and apparatus for identifying a first flow control instruction in an executing program, the first instruction being associated with a first program address at which program execution will...
7603544 Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
7519777 Methods, systems and computer program products for concomitant pair prefetching  
Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride...
7516313 Predicting contention in a processor  
In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction,...
7496905 System and method for generating state machines  
The present invention generates state machines that can be used in a scanner and/or a parser for software program compilation. The state machines are not table-driven, but rather are encoded...
7472262 Methods and apparatus to prefetch memory objects by predicting program states based on entropy values  
Methods and apparatus are disclosed to prefetch memory objects. An example method includes identifying program states associated with an executing program; associating memory profiles with...
7451299 System and method for generating multi-way branches  
State machines can be used in a scanner and a parser for program compilation. The state machines can be non-table-driven, but rather are encoded directly in bytecodes. A special algorithm can be...
7257665 Branch-aware FIFO for interprocessor data sharing  
A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations...
7167973 Method and system for performing multi-tests in processors using results to set a register and indexing based on the register  
A microprocessor, including a plurality of registers and an instruction execution module which is adapted to process a sequence of conditional tests. The module uses an instruction set that has the...
7165169 Speculative branch target address cache with selective override by secondary predictor based on branch instruction type  
A branch prediction apparatus having a primary predictor and a secondary predictor that selectively overrides the primary predictor based on the type of branch instruction decoded. A branch target...
7136992 Method and apparatus for a stew-based loop predictor  
A method and apparatus for a loop predictor for predicting the end of a loop is disclosed. In one embodiment, the loop predictor may have a predict counter to hold a predict count representing the...
7082520 Branch prediction utilizing both a branch target buffer and a multiple target table  
Improved Branch prediction utilizes both a Branch Target Buffer (BTB) and a Multiple Target Table (MTT) for providing the capability to predict multiple targets for a single branch. A MTT when used...
6983361 Apparatus and method for implementing switch instructions in an IA64 architecture  
An apparatus and method for implementing a switch instruction in the IA 64 architecture is provided. With the apparatus and method, a first register is used to identify whether a low is either 0,...
6968545 Method and apparatus for no-latency conditional branching  
An apparatus to perform no-latency conditional branching has a sequencer for executing program instructions including one or more conditional branch instructions. The conditional branch instruction...
6968542 Method for dynamically identifying pseudo-invariant instructions and their most common output values on frequently executing program paths  
A method of identifying pseudo-invariant instructions in computer program hot paths, comprising the steps of creating an intermediate representation of a hot path in a software buffer, executing...
6925591 Method and apparatus for providing full accessibility to instruction cache and microcode ROM  
A method and apparatus for providing full accessibility to on-chip instruction cache and microcode ROM are described. A dummy tag and a dummy instruction are written into a cache tag array and an...
6857063 Data processor and method of operation  
A data processor executes an instruction (JAVASW) to implement efficient interpreter functionality by combining the tasks of table jumps and thread or task switching which is controlled by a...
6851046 Jumping to a recombine target address which is encoded in a ternary branch instruction  
A system and method for performing a general ternary branch instruction is provided. Additionally, different approaches are provided for reducing the complexity of a ternary branch instruction word...
6845463 System for contracting out part of accepted request  
An order placement and acceptance system includes a first data processing device for sending a design data for processing and manufacture of a predetermined item, a second data processing device...
6810474 Information processor  
In a conventional information processor that performs speculative execution of a following instruction having a data dependency, since an arithmetic and logical unit is used in performing the...
6766447 System and method of preventing speculative reading during memory initialization  
A method of initializing random access memory during a BIOS process executed by a processor that is configured to perform speculative reading. The ROM BIOS is modified such that speculative reading...
6728949 Method and system for periodic trace sampling using a mask to qualify trace data  
A method and system for monitoring execution performance of a program is provided. Profiling functionality may be qualified by setting various qualifying flags at the request of a user. These...
6675291 Hardware device for parallel processing of any instruction within a set of instructions  
Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined...
6662296 Method and system for testing millicode branch points  
An exemplary embodiment of the present invention is a method and system for reducing the number of branch instructions required to test combinations of millicode branch points. The method is...
6654877 System and method for selectively executing computer code  
A system of the present invention utilizes memory for storing a computer program and processing circuitry for processing and executing instructions of the computer program. In particular, the...
6578134 Multi-branch resolution  
A branch resolution logic for an in-order processor is provided which scans the stages of processor pipeline to determine the oldest branch instruction having sufficient condition codes for...
6553426 Method apparatus for implementing multiple return sites  
Methods and apparatus for efficiently enabling an alternate return address associated with a function call to essentially be stored such that the alternate return address may be readily accessed...
6550004 Hybrid branch predictor with improved selector table update mechanism  
A branch predictor for improving branch prediction accuracy is provided. The branch predictor includes global and local Agree dynamic branch predictors, one of which is selected for correlation...
6546359 Method and apparatus for multiplexing hardware performance indicators  
In accordance with methods and systems consistent with the present invention, an improved processor performance instrumentation system is provided that allows a software tester to measure more...
6526502 Apparatus and method for speculatively updating global branch history with branch prediction prior to resolution of branch outcome  
An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively...
6457120 Processor and method including a cache having confirmation bits for improving address predictable branch instruction target predictions  
A superscalar processor and method are disclosed for improving the accuracy of predictions of a destination of a branch instruction utilizing a cache. The cache is established including multiple...
6449714 Total flexibility of predicted fetching of multiple sectors from an aligned instruction cache for instruction execution  
Each of plural rows in an aligned Instruction cache (AIC) contains a plurality of aligned sectors, each sector having space for a block of sequentially-addressed instructions in an executing...
6446196 Method apparatus and computer program product including one-of and one-of-and-jump instructions for processing data communications  
A method, apparatus and computer program product are provided including one-of and one-of-and-jump instructions for use with processing data communications in a communications system. A one-of...
6427206 Optimized branch predictions for strongly predicted compiler branches  
A microprocessor is disclosed. The microprocessor includes a branch prediction table that has at least one branch entry. The at least one branch entry includes a prediction field to indicate...
6381691 Method and apparatus for reordering memory operations along multiple execution paths in a processor  
A method is provided for scheduling instructions for execution along multiple paths in a Computer processing system implementing out-of-order execution. The method includes the step of selecting...
6378066 Method, apparatus, and article of manufacture for developing and executing data flow programs, and optimizing user input specifications  
Methods, systems, and articles of manufacture consistent with the present invention provide a development tool that enables computer programmers to design and develop a data flow program for...
6367004 Method and apparatus for predicting a predicate based on historical information and the least significant bits of operands to be compared  
In one method, a predicted predicate value may be determined. A predicated instruction is then conditionally executed depending on the predicted predicate value. For example, in accordance with one...
6356918 Method and system for managing registers in a data processing system supports out-of-order and speculative instruction execution  
A method and a system in a data processing system for managing registers in a register array wherein the data processing system has M architected registers and the register array has greater than M...
6351796 Methods and apparatus for increasing the efficiency of a higher level cache by selectively performing writes to the higher level cache  
Methods and apparatus for storing data in a multi-level memory hierarchy having at least a lower level cache and a higher level cache. Relevancy information is maintained for various data values...
6334184 Processor and method of fetching an instruction that select one of a plurality of decoded fetch addresses generated in parallel to form a memory request  
A processor and method of fetching an instruction from a memory are disclosed. According to the method of the present invention, a plurality of target addresses are determined utilizing a plurality...
6330662 Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures  
An instruction fetch unit for fetching instructions from an instruction cache of a processor. The fetch unit includes a next fetch address mechanism generating predicted next fetch addresses, the...
6330692 Method of determining the route to be tested in a load module test  
A method of determining a route to be tested in the testing of a load module which includes a multiplicity of routes (route patterns) from the start to the end of the program, each route pattern...
6304960 Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions  
A system for validating branch predictions for clusters of branch instructions includes an address validation module and a condition validation module. The address validation module determines...
6282663 Method and apparatus for performing power management by suppressing the speculative execution of instructions within a pipelined microprocessor  
A method for reducing power consumption within a processor, having branch prediction circuitry, requires detecting the occurrence of a trigger event and then suppressing speculative execution of an...
6279107 Branch selectors associated with byte ranges within an instruction cache for rapidly identifying branch predictions  
A branch prediction unit stores a set of branch selectors corresponding to each of a group of contiguous instruction bytes stored in an instruction cache. Each branch selector identifies the branch...
6263427 Branch prediction mechanism  
A branch prediction mechanism for predicting the outcome and the branch target address of the next possible branch instruction of a current instruction. Each of the entry of the branch target...
6256728 Processor configured to selectively cancel instructions from its pipeline responsive to a predicted-taken short forward branch instruction  
A processor is configured to detect a branch instruction have a forward branch target address within a predetermined range of the branch fetch address of the branch instruction. If the branch...
6247146 Method for verifying branch trace history buffer information  
A method and system for verifying the accuracy of trace data generated by execution of a program on a computer under test, one embodiment of the method comprising scanning the trace data to locate...
6243805 Programming paradigm and microprocessor architecture for exact branch targeting  
A microprocessor for executing exact branch targeting is disclosed. A microprocessor contains a fetch stage for fetching and receiving instructions from memory at a memory address specified by a...
Matches 1 - 50 out of 121 1 2 3 >