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8949806 Compiling code for parallel processing architectures based on control flow  
A system comprises a plurality of computation units interconnected by an interconnection network. A method for configuring the system comprises forming subsets of instructions corresponding to...
8909906 Packet processor configured for processing features directed by branch instruction with logical operator and two feature selector fields  
A method and apparatus for branch reduction in a multithreaded packet processor is presented. An instruction is executed which includes testing of a branch flag. The branch flag references a...
8677104 System for efficiently tracing data in a data processing system  
A data processing apparatus is provided comprising prediction circuitry for predicting a response of the data processing circuitry at at least one given execution point to execution of a program...
8677106 Unanimous branch instructions in a parallel thread processor  
One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed,...
8656144 Image processing device, image processing method, and image processing program  
The invention provides an image processing device, an image processing method, and an image processing program which enable accurately observing a moving image of an object within a time interval...
8601177 Dynamic allocation of a buffer across multiple clients in a threaded processor  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
8595473 Method and apparatus for performing control of flow in a graphics processor architecture  
Methods and systems for performing control of flow in a graphics processor architecture are provided. For example, in at least one embodiment, a computing system includes a memory storing a...
8554545 Methods and apparatus to extract data encoded in media content  
Methods and apparatus to extract data encoded in media content are disclosed. An example method includes sampling a media content signal to generate digital samples, determining a frequency domain...
8539501 Managing access to a shared resource in a data processing system  
Processes requiring access to shared resources are adapted to issue a reservation request, such that a place in a resource access queue, such as one administered by means of a semaphore system,...
8522250 Managing access to a shared resource in a data processing system  
Processes requiring access to shared resources are adapted to issue a reservation request, such that a place in a resource access queue, such as one administered by means of a semaphore system,...
8516195 Extract cache attribute facility and instruction therefore  
A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or...
8516229 Two pass test case generation using self-modifying instruction replacement  
A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent...
8417923 Data processing apparatus having trace and prediction logic  
A data processing apparatus is disclosed including trace logic for monitoring behavior of a portion of said data processing apparatus and prediction logic for providing at least one prediction as...
8392893 Emulation method and computer system  
The computer system of the present invention emulates target instructions. The computer system includes a processing unit for branching to collective emulation coding for emulating plural of...
8332622 Branching to target address by adding value selected from programmable offset table to base address specified in branch instruction  
Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition...
8239847 General distributed reduction for data parallel computing  
General-purpose distributed data-parallel computing using high-level computing languages is described. Data parallel portions of a sequential program written in a high-level language are...
8225012 Dynamic allocation of a buffer across multiple clients in a threaded processor  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
8131934 Extract cache attribute facility and instruction therefore  
A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or...
8078849 Fast execution of branch instruction with multiple conditional expressions using programmable branch offset table  
Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition...
8069339 Microprocessor with microinstruction-specifiable non-architectural condition code flag register  
A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set...
8019979 Efficient implementation of branch intensive algorithms in VLIW and superscalar processors  
An apparatus for implementing branch intensive algorithms is disclosed. The apparatus includes a processor containing a plurality of ALUs and a plurality of result registers. Each result register...
7970723 Defining extensible expression behavior in a rules system  
Described herein is technology for, among other things, enabling use of custom expressions in a rules engine. The rules engine may be used in conjunction with a workflow. The technology involves...
7937572 Run-time selection of feed-back connections in a multiple-instruction word processor  
A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue...
7904698 Electronic parallel processing circuit for performing jump instructions  
The electronic circuit contains a plurality of processing elements (10), which are supplied with instructions under control of a common program flow, typically for SIMD operation wherein the same...
7886132 Predication support in an out-of-order processor by selectively executing ambiguously renamed write operations  
A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that...
7870339 Extract cache attribute facility and instruction therefore  
A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or...
7818552 Operation, compare, branch VLIW processor  
A VLIW processor is provided with an architecture which includes fetching and executing circuitry which when combined with operation, compare, branch (OCB) instructions realizes no processing...
7797519 Processor apparatus with instruction set for storing comparison conditions and for evaluating branch condition values against results of identified complex comparison conditions  
There is disclosed a processing apparatus including, as an instruction set, a complex conditional branch instruction, and a condition setting instruction. The complex conditional branch...
7793084 Efficient handling of vector high-level language conditional constructs in a SIMD processor  
The present invention provides an efficient method to implement nested if-then-else conditional statements in a SIMD processor, which requires only one vector compare instruction for both if and...
7761697 Processing an indirect branch instruction in a SIMD architecture  
One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The...
7725694 Processor, microcomputer and method for controlling program of microcomputer  
A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a...
7711936 Branch predictor for branches with asymmetric penalties  
An approach for improving efficiency of speculative execution of instructions is disclosed. In one embodiment, a branch predictor entry associated with a particular branch instruction is accessed...
7647488 Information processing device with branch history restoration  
The information processing device of the present invention stores the branch history information of a fetched instruction. When branch prediction fails, BHR information used for the branch...
7634644 Effective elimination of delay slot handling from a front section of a processor pipeline  
Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution...
7613907 Embedded software camouflage against code reverse engineering  
Methods and apparatus for identifying a first flow control instruction in an executing program, the first instruction being associated with a first program address at which program execution will...
7603544 Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
7519777 Methods, systems and computer program products for concomitant pair prefetching  
Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride...
7516313 Predicting contention in a processor  
In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction,...
7496905 System and method for generating state machines  
The present invention generates state machines that can be used in a scanner and/or a parser for software program compilation. The state machines are not table-driven, but rather are encoded...
7472262 Methods and apparatus to prefetch memory objects by predicting program states based on entropy values  
Methods and apparatus are disclosed to prefetch memory objects. An example method includes identifying program states associated with an executing program; associating memory profiles with...
7451299 System and method for generating multi-way branches  
State machines can be used in a scanner and a parser for program compilation. The state machines can be non-table-driven, but rather are encoded directly in bytecodes. A special algorithm can be...
7257665 Branch-aware FIFO for interprocessor data sharing  
A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory...
7167973 Method and system for performing multi-tests in processors using results to set a register and indexing based on the register  
A microprocessor, including a plurality of registers and an instruction execution module which is adapted to process a sequence of conditional tests. The module uses an instruction set that has...
7165169 Speculative branch target address cache with selective override by secondary predictor based on branch instruction type  
A branch prediction apparatus having a primary predictor and a secondary predictor that selectively overrides the primary predictor based on the type of branch instruction decoded. A branch target...
7136992 Method and apparatus for a stew-based loop predictor  
A method and apparatus for a loop predictor for predicting the end of a loop is disclosed. In one embodiment, the loop predictor may have a predict counter to hold a predict count representing the...
7082520 Branch prediction utilizing both a branch target buffer and a multiple target table  
Improved Branch prediction utilizes both a Branch Target Buffer (BTB) and a Multiple Target Table (MTT) for providing the capability to predict multiple targets for a single branch. A MTT when...
6983361 Apparatus and method for implementing switch instructions in an IA64 architecture  
An apparatus and method for implementing a switch instruction in the IA64 architecture is provided. With the apparatus and method, a first register is used to identify whether a low is either 0, 1...
6968542 Method for dynamically identifying pseudo-invariant instructions and their most common output values on frequently executing program paths  
A method of identifying pseudo-invariant instructions in computer program hot paths, comprising the steps of creating an intermediate representation of a hot path in a software buffer, executing...
6968545 Method and apparatus for no-latency conditional branching  
An apparatus to perform no-latency conditional branching has a sequencer for executing program instructions including one or more conditional branch instructions. The conditional branch...
6925591 Method and apparatus for providing full accessibility to instruction cache and microcode ROM  
A method and apparatus for providing full accessibility to on-chip instruction cache and microcode ROM are described. A dummy tag and a dummy instruction are written into a cache tag array and an...

Matches 1 - 50 out of 154 1 2 3 4 >