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7610473 Apparatus, method, and instruction for initiation of concurrent instruction streams in a multithreading microprocessor  
A fork instruction for execution on a multithreaded microprocessor and occupying a single instruction issue slot is disclosed. The fork instruction, executing in a parent thread, includes a first...
7603544 Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
7574588 Time-multiplexed speculative multi-threading to support single-threaded applications  
One embodiment of the present invention provides a system that facilitates interleaved execution of a head thread and a speculative thread within a single processor pipeline. The system operates by...
7519777 Methods, systems and computer program products for concomitant pair prefetching  
Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride...
7502910 Sideband scout thread processor for reducing latency associated with a main processor  
A sideband scout thread processing technique is provided. The sideband scout thread processing technique utilizes sideband information to identify a subset of processor instructions for execution...
7500087 Synchronization of parallel processes using speculative execution of synchronization instructions  
A speculative execution capability of a processor is exposed to program control through at least one machine instruction. The at least one machine instruction may be two instructions designed to...
7454601 N-wide add-compare-select instruction  
The present invention relates to a method and system for providing an N-wide add-compare-select instruction includes decoding an instruction as an N-wide add-compare-select instruction and...
7421572 Branch instruction for processor with branching dependent on a specified bit in a register  
A processor such as a parallel hardware-based multithreaded processor ( 12 ) is described. The processor ( 12 ) can execute a computer instruction that is a branch instruction that causes an...
7409535 Branch target prediction for multi-target branches by identifying a repeated pattern  
An information processing system for branch target prediction is disclosed. The information processing system includes a memory for storing entries, wherein each entry includes a plurality of...
7363474 Method and apparatus for suspending execution of a thread until a specified memory access occurs  
Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A...
7302556 Method, apparatus and computer program product for implementing level bias function for branch prediction control for generating test simulation vectors  
A method, apparatus and computer program product are provided for implementing a level bias function for branch prediction control for generating test simulation vectors. User selected options are...
7281122 Method and apparatus for nested control flow of instructions using context information and instructions having extra bits  
A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction...
7281120 Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor  
A method and apparatus for executing instructions in a pipeline processor. The method decreases the latency between an instruction cache and a pipeline processor when bubbles occur in the...
7260706 Branch misprediction recovery using a side memory  
A mispredicted path side memory is configured to be coupled to a stage in an instruction pipeline. As instructions advance through the pipeline, a result from the stage is stored into the...
7257700 Avoiding register RAW hazards when returning from speculative execution  
One embodiment of the present invention provides a system that avoids register read-after-write (RAW) hazards upon returning from a speculative-execution mode. This system operates within a...
7152170 Simultaneous multi-threading processor circuits and computer program products configured to operate at different performance levels based on a number of operating threads and methods of operating  
Processing circuits that are associated with the operation of threads in an SMT processor can be configured to operate at different performance levels based on a number of threads currently...
7139902 Implementation of an efficient instruction fetch pipeline utilizing a trace cache  
A method and apparatus are disclosed for enhancing the pipeline instruction transfer and execution performance of a computer architecture by reducing instruction stalls due to branch and jump...
7134004 Processing device for buffering sequential and target sequences and target address information for multiple branch instructions  
An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which...
7114063 Condition indicator for use by a conditional branch instruction  
A branch prediction method and system are provided that accurately predict a branch condition early in an instruction pipeline of a data processing system. By accurately predicting the branch...
7111296 Thread signaling in multi-threaded processor  
A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support...
7082519 System and method for instruction level multithreading scheduling in a embedded processor  
A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous...
7065636 Hardware loops and pipeline system using advanced generation of loop parameters  
In one embodiment, a programmable processor is adapted to support hardware loops. The processor may include hardware such as a first set of registers, a second set of registers, a first pipeline,...
7051195 Method of optimization of CPU and chipset performance by support of optional reads by CPU and chipset  
In processing an instruction request, the invention determines whether the request is speculative or not based upon a bit field within the instruction. If the request is speculative, bus congestion...
7047399 Computer system and method for fetching, decoding and executing instructions  
A computer system for executing branch instructions and a method of executing branch instructions are described. Two instruction fetchers respectively fetch a sequence of instructions from memory...
7010675 Fetch branch architecture for reducing branch penalty without branch prediction  
In lieu of branch prediction, a merged fetch-branch unit operates in parallel with the decode unit within a processor. Upon detection of a branch instruction within a group of one or more fetched...
7003649 Control forwarding in a pipeline digital processor  
A data processor includes at least one instruction pipeline for executing an instruction stream having branch instructions. The choices of a branch instruction, the next inline instruction or a...
6988189 Ternary content addressable memory based multi-dimensional multi-way branch selector and method of operating same  
An embodiment of the present invention described and shown in the specification and drawing is a Ternary Content Addressable Memory (TCAM) multi-dimensional multi-way branch selector. The...
6976156 Pipeline stall reduction in wide issue processor by providing mispredict PC queue and staging registers to track branch instructions in pipeline  
For use in a wide-issue pipelined processor, a mechanism for, and method of, reducing pipeline stalls between conditional branches and a digital signal processor (DSP) incorporating the mechanism...
6968447 System and method for data forwarding in a programmable multiple network processor environment  
A system and method forward data between processing elements. A first processing element includes an address register that stores a first memory address. A forwarding storage element is coupled to...
6961847 Method and apparatus for controlling execution of speculations in a processor based on monitoring power consumption  
In accordance with one embodiment, the invention provides a method comprising monitoring a power consumption of a processor in executing a program while running in a speculative execution mode...
6950927 System and method for instruction-level parallelism in a programmable multiple network processor environment  
A system and method process data elements with instruction-level parallelism. An instruction buffer holds a first instruction and a second instruction, the first instruction being associated with a...
6928645 Software-based speculative pre-computation and multithreading  
Speculative pre-computation and multithreading (SP), allows a processor to use spare hardware contexts to spawn speculative threads to very effectively pre-fetch data well in advance of the main...
6895473 Data control device and an ATM control device  
A data control device capable of high-quality, high-efficiency control for speeding up data processing, thus permitting improvement of the throughput of a system. Attribute analyzing unit analyzes...
6880073 Speculative execution of instructions and processes before completion of preceding barrier operations  
Described is a data processing system and processor that provides full multiprocessor speculation by which all instructions subsequent to barrier operations in a instruction sequence are...
6877088 Methods and apparatus for controlling speculative execution of instructions based on a multiaccess memory condition  
Mechanisms and techniques operate in a computerized device to enable or disable speculative execution of instructions such as reordering of load and store instructions a multiprocessing...
6842846 Instruction pre-fetch amount control with reading amount register flag set based on pre-detection of conditional branch-select instruction  
An architecture of method for fetching microprocessor's instructions is provided to pre-fetch and pre-decode a next instruction. If the instruction pre-decoded is found a conditional branch...
6823473 Simultaneous and redundantly threaded processor uncached load address comparator and data value replication circuit  
A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead...
6817013 Program optimization method, and compiler using the same  
An optimization method and apparatus for converting source code for a program written in a programming language into machine language. The program includes a basic block as a unit to estimate an...
6799263 Prefetch instruction for an unpredicted path including a flush field for indicating whether earlier prefetches are to be discarded and whether in-progress prefetches are to be aborted  
A method for prefetching instructions into cache memory using a prefetch instruction. The prefetch instruction contains a target field, a count field, a cache level field, a flush field, and a...
6792525 Input replicator for interrupts in a simultaneous and redundantly threaded processor  
A processor is disclosed having a fetch unit that initiating interrupt service routines in redundant, unsynchronized threads. A counter is provided to track the difference between leading and...
6792524 System and method cancelling a speculative branch  
For each predicted branch within a processor, an entry is maintained within a branch history table. The entry within the branch history table also includes an indication of the past record for that...
6782463 Shared memory array  
Disclosed is a device comprising a core processing circuit coupled to a single memory array which is partitioned into at least a first portion as a cache memory of the core processing circuit, and...
6772324 Processor having multiple program counters and trace buffers outside an execution pipeline  
In one embodiment of the invention, a processor includes an execution pipeline to concurrently execute at least portions of threads, wherein at least one of the threads is dependent on at least...
6766447 System and method of preventing speculative reading during memory initialization  
A method of initializing random access memory during a BIOS process executed by a processor that is configured to perform speculative reading. The ROM BIOS is modified such that speculative reading...
6725338 Method and apparatus for preventing cache pollution in microprocessors with speculative address loads  
A method of optimizing speculative address load processing by a microprocessor includes identifying a speculative load, marking the speculative load, determining whether a miss occurs for the...
6715065 Micro program control method and apparatus thereof having branch instructions  
In an information processing apparatus which executes micro programs having branch instructions, two micro instructions are read at once, each of which instructions comprises either a field for...
6714961 Multiple job signals per processing unit in a multiprocessing system  
The invention is directed toward a multiprocessing system having multiple processing units. For at least one of the processing units in the multiprocessing system, a first job signal is assigned to...
6691220 Multiprocessor speculation mechanism via a barrier speculation flag  
A method of operation within a processor that permits load instructions following barrier instructions in an instruction sequence to be issued speculatively. The barrier instruction is executed and...
6687812 Parallel processing apparatus  
Disclosed is a parallel processing apparatus capable of reducing power consumption by efficiently executing a fork instruction for activating a plurality of processors. The parallel processing...
6675374 Insertion of prefetch instructions into computer program code  
A technique is provided for inserting memory prefetch instructions only at appropriate locations in program code. The instructions are inserted into the program code such that, when the code is...
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