Matches 101 - 146 out of 146 < 1 2 3
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5961637 Split branch system utilizing separate set branch, condition and branch instructions and including dual instruction fetchers  
A computer system for executing branch instructions and a method of executing branch instructions are described. Tow instruction fetchers respectively fetch a sequence of instructions from memory...
5928357 Circuitry and method for performing branching without pipeline delay  
The pipeline architecture minimizes delays incurred during execution of branch instructions. While a first instruction is executing, a second instruction is fetched and is ready for execution at...
5926645 Method and system for enabling multiple store instruction completions in a processing system  
A method and system for a handling multiple store instruction completions in a processing system after a stall condition is disclosed. The processing system includes an instruction unit, the...
5918044 Apparatus and method for instruction fetching using a multi-port instruction cache directory  
In an instruction fetch unit for an information handling system which decodes instructions, calculates target addresses of multiple branch instructions, and resolves multiple branch instructions in...
5889966 Data processor having bus controller for controlling a plurality of buses independently of each other  
A data processor has a memory 100 for storing instructions being connected to a microcomputer 10 having a function of fetching an instruction from an external memory 100 via an external bus 95, a...
5850542 Microprocessor instruction hedge-fetching in a multiprediction branch environment  
An apparatus for fetching instructions in a computer system is disclosed. The apparatus includes a cache circuit for holding a sub-set of main store, a buffer circuit for holding instructions...
5850543 Microprocessor with speculative instruction pipelining storing a speculative register value within branch target buffer for use in speculatively executing instructions after a return  
A microprocessor of the superscalar pipelined type, having speculative execution capability, is disclosed. Speculative execution is under the control of a fetch unit having a branch target buffer...
5838940 Method and apparatus for rotating active instructions in a parallel data processor  
In a microprocessor, apparatus and method coordinate the fetch and issue of instructions by rotating multiple, fetched instructions into an issue order prior to issuance and dispatching selected of...
5822574 Functional unit with a pointer for mispredicted resolution, and a superscalar microprocessor employing the same  
A superscalar microprocessor is provided having functional units which receive a pointer (a reorder buffer tag) which is compared to the reorder buffer tags of the instructions currently being...
5812839 Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit  
A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch...
5812837 Data processing apparatus for controlling an interrupt process and its method  
An interrupt processing apparatus is set if an interrupt factor occurs during execution of a moved instruction. The interrupt processing unit generates an interrupt single when processing after...
5809294 Parallel processing unit which processes branch instructions without decreased performance when a branch is taken  
A parallel processing unit operable in a delayed branch method has a branch-delay slot filled with instructions to be executed when a branch by a branch instruction is taken. The instructions in...
5774685 Method and apparatus for biasing cache LRU for prefetched instructions/data based upon evaluation of speculative conditions  
The computer processing unit of the present invention includes a new prefetch instruction, referred to as an STOUCH instruction, which provides the capability to encode compile-time speculations...
5729707 Instruction prefetch circuit and cache device with branch detection  
In an instruction prefetch circuit, even when a branch instruction is prefetched, the circuit continues a prefetch operation until branching is actually executed. Accordingly, when the branch...
5717883 Method and apparatus for parallel execution of computer programs using information providing for reconstruction of a logical sequential program  
A computer system with multiple execution units operates by treating a logical program as a tree structure with segments which include several computer instructions. Segments of the tree structure...
5696958 Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline  
A pipeline processor, when processing a branch instruction, initiates fetching of both the target and fall-through streams prior to execution of the branch instruction such that the number of...
5659722 Multiple condition code branching system in a multi-processor environment  
A data processing system includes a number of processing elements wherein each of the processing elements generates one or more condition signals, one or more memory elements associated with the...
5640584 Virtual processor method and apparatus for enhancing parallelism and availability in computer systems  
A virtual processor method and apparatus for parallel computer systems that increases the level of parallelism to include multiple threads per node. If a processor node has a plurality of storage...
5634103 Method and system for minimizing branch misprediction penalties within a processor  
A method and system within a processor are disclosed for executing selected instructions among a number of instructions stored within a memory, wherein the processor has a maximum of instructions...
5600842 Microprogram controller for controlling readout of a microprogram stored in multiple storage areas  
Connecting an address register and a read register to each of a main control storage and an external control storage to transfer an output from the read register of the external control storage to...
5586278 Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor  
A method of state recovery following a branch misprediction or an undetected branch instruction. If, during execution of a branch instruction in an out-of-order unit, it is determined that the...
5553255 Data processor with programmable levels of speculative instruction fetching and method of operation  
A data processor (12) has a branch prediction unit (28) that predicts conditional branch instructions and a control unit (70) therein that monitors the number of unresolved branch instructions....
5522084 Method and system for invalidating instructions utilizing validity and write delay flags in parallel processing apparatus  
A superscalar-type processor includes an instruction memory, a fetch stage fetching simultaneously a plurality of instructions from the instruction memory, functional units respectively executing...
5511172 Speculative execution processor  
The present invention discloses a speculative execution processor including a plurality of executing units for processing in parallel a plurality of instructions in an instruction sequence stored...
5471593 Computer processor with an efficient means of executing many instructions simultaneously  
To increase the performance of a pipelined processor executing instructions, conditional instruction execution issues and executes instructions, including but not limited to branches, before the...
5461722 Parallel processing apparatus suitable for executing in parallel a plurality of instructions including at least two branch instructions  
A parallel processing apparatus suitable when a plurality of instructions including at least two branch instructions are parallelly executed is disclosed. This invention is provided with a register...
5453927 Data processor for processing branch instructions  
A data processor capable of efficiently processing jump instructions including an instruction fetch unit for fetching instructions from a memory, an instruction decoding unit for decoding...
5450556 VLIW processor which uses path information generated by a branch control unit to inhibit operations which are not on a correct path  
A highly parallel and pipelined computer processor such as a pipelined very long instruction word (VLIW) processor having a plurality of arithmetic and logic units (ALUs) which process computer...
5404551 Parallel processor which processes instructions, after a branch instruction, in parallel prior to executing the branch instruction and its parallel processing method  
In a typical operating system, one-third of a program consists of branch instructions. This means a performance of a processor of a typical operating system depends greatly on whether or not an...
5396640 Boosting method and apparatus in a parallel computer  
A parallel computer having a boosting function in which an instruction belonging to a later basic block is moved to a precedent basic block in an instruction group, the moved basic block being a...
5381531 Data processor for selective simultaneous execution of a delay slot instruction and a second subsequent instruction the pair following a conditional branch instruction  
An instruction fetch unit (640) of a data processor (610) capable of simultaneous execution of two instructions fetches a first and a second instruction from a memory (620) in one cycle. The first...
5353419 Memory-side driven anticipatory instruction transfer interface with processor-side instruction selection  
A computer architecture which significantly reduces latency in fetching instructions from main memory includes a code-pump located proximate to the memory and a filter cache located proximate to...
5327567 Method and system for returning emulated results from a trap handler  
A trap handler return for returning emulated results from a trap handler in a data processor includes source and destination register sets, and circuitry for transferring a specified value from the...
5287467 Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit  
The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected...
5269007 RISC system capable of simultaneously executing data interlocked shift and arithmetic/logic instructions in one clock cycle by bypassing register  
First and second instructions are simultaneously fetched from a memory to be respectively decoded by first and second instruction decoders. An instruction execution unit includes a register file,...
5267350 Method for fetching plural instructions using single fetch request in accordance with empty state of instruction buffers and setting of flag latches  
An instruction fetch control method is generally arranged so as to have a plurality of instruction buffers, issue an instruction read request to a memory when a part of the instruction buffers...
5165025 Interlacing the paths after a conditional branch like instruction  
By interlacing the two program paths after the test part of a conditional branch, both program paths are available (with minimal delay) from a simple instruction fetch mechanism. Further, the...
4991080 Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions  
In an approach to reducing delays resulting from resolution of conditional branch instructions, such instructions are pre-executed in a coprocessor which precedes a pipeline processor and prepared...
4985826 Method and device to execute two instruction sequences in an order determined in advance  
A data processing system executes two instruction sequences in an order determined in advance. Each sequence is stored in a separate memory. Data information used in the second sequence is not...
4858105 Pipelined data processor capable of decoding and executing plural instructions in parallel  
A pipelined data processor comprises a circuit for storing two instructions in a pair of instruction registers, a circuit for detecting whether those instructions are a combination of an...
4777587 System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses  
An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor...
4748585 Processor utilizing reconfigurable process segments to accomodate data word length  
An independently programmable, parallel processor for electronic computers for performing mathematical and logical operations is provided having an array of arithmetic-logic units which are...
4742451 Instruction prefetch system for conditional branch instruction for central processor unit  
A central processor unit for a digital data processing system that processes prefetched instructions including a conditional branch instruction. The processor includes a fetch unit that has...
4439827 Dual fetch microsequencer  
A dual fetch microsequencer having two single-ported microprogram memories wherein both the sequential and jump address microinstructions of a binary conditional branch can be simultaneously...
4200927 Multi-instruction stream branch processing mechanism  
In a high-performance computer which prefetches and predecodes instructions for sequential presentation to an execution unit, at least three separately gated and sequenced multi-instruction buffers...
4155120 Apparatus and method for controlling microinstruction sequencing by selectively inhibiting microinstruction execution  
A microprogrammed digital computer employing a plurality of programmable read only memories containing stored control words which are specially chosen so as to provide for microinstruction...
Matches 101 - 146 out of 146 < 1 2 3