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8966324 Transactional execution branch indications  
Transactional execution branch indications are placed into one or more transaction diagnostic blocks when a transaction is aborted. Each branch indication specifies whether a branch was taken, as...
8959500 Pipelined processor and compiler/scheduler for variable number branch delay slots  
Different numbers of delay slots are assigned by a compiler/scheduler to each different type of jump operation in a pipelined processor system. The number of delay slots is variable and kept to...
8959319 Executing first instructions for smaller set of SIMD threads diverging upon conditional branch instruction  
Embodiments of the present invention provide systems, methods, and computer program products for improving divergent conditional branches in code being executed by a processor. For example, in an...
8954940 Integrating preprocessor behavior into parsing  
A method, computer program product, and system is described. Software code text associated with a software code editor and including one or more preprocessor statements is identified. The software...
8943298 Meta predictor restoration upon detecting misprediction  
Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register...
8930760 Validating cache coherency protocol within a processor  
A mechanism is provided for effectively validating cache coherency within a processor. For each node in a set of nodes, responsive to a node in a set of nodes being a controlling node, at least...
8914622 Processor testing  
Processors may be tested according to various implementations. In one general implementation, a process for processor testing may include randomly generating a first plurality of branch...
8909906 Packet processor configured for processing features directed by branch instruction with logical operator and two feature selector fields  
A method and apparatus for branch reduction in a multithreaded packet processor is presented. An instruction is executed which includes testing of a branch flag. The branch flag references a...
8892949 Effective validation of execution units within a processor  
A mechanism is provided for effectively validating execution units within a processor. A branch test pattern is generated for execution by an execution unit that is under validation testing. An...
8887002 Transactional execution branch indications  
Transactional execution branch indications are placed into one or more transaction diagnostic blocks when a transaction is aborted. Each branch indication specifies whether a branch was taken, as...
8850436 Opcode-specified predicatable warp post-synchronization  
One embodiment of the present invention sets forth a technique for performing a method for synchronizing divergent executing threads. The method includes receiving a plurality of instructions that...
8832417 Program flow control for multiple divergent SIMD threads using a minimum resume counter  
This disclosure describes techniques for handling divergent thread conditions in a multi-threaded processing system. In some examples, a control flow unit may obtain a control flow instruction...
8819399 Predicated control flow and store instructions for native code module security  
Some embodiments provide a system that executes a native code module. During operation, the system obtains the native code module. Next, the system loads the native code module into a secure...
8813057 Branch pruning in architectures with speculation support  
According to one example embodiment of the inventive subject matter, the method and apparatus described herein is used to generate an optimized speculative version of a static piece of code. The...
8812826 Processor testing  
In one implementation, processor testing may include the ability to randomly generate a first plurality of branch instructions for a first portion of an instruction set, each branch instruction in...
8806183 Blank bit and processor instructions employing the blank bit  
Reading a value into a register, checking to see if the value is a NULL, and then jumping out of a loop if the value is a NULL is a common task that processors perform. To speed performance of...
8799628 Early branch determination  
A method and apparatus for branch determination is disclosed. The method includes a first command issuing within a computer processor. Execution of the first command by the computer processor...
8751823 System and method for branch function based obfuscation  
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for obfuscating branches in computer code. A compiler or a post-compilation tool can obfuscate branches by...
8751776 Method for predicting branch target address based on previous prediction  
A branch target address table is provided for each branch instruction having a plurality of branch targets. Each branch target address table stores a history of a plurality of branch target...
8707424 Method for making secure execution of a computer programme, in particular in a smart card  
A method for making secure execution of a computer program includes the following steps: stacking a predetermined value in a pile of instructions of the program; and stack popping the pile, the...
8667259 Data processor and memory read active control method  
Instruction cache memory having a plurality of memory (for example, cache WAY), means 3 for storing prediction data of a conditional branch of a branch instruction being taken or not taken and for...
8656400 Synchronisation of execution threads on a multi-threaded processor  
Method and apparatus are provided for a synchronizing execution of a plurality of threads on a multi-threaded processor. Each thread is provided with a number of synchronization points...
8621187 Method of program obfuscation and processing device for executing obfuscated programs  
A program is obfuscated by reordering its instructions. Original instruction addresses are mapped to target addresses. A cache efficient obfuscated program is realized by restricting target...
8615646 Unanimous branch instructions in a parallel thread processor  
One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed,...
8601177 Dynamic allocation of a buffer across multiple clients in a threaded processor  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
8572358 Meta predictor restoration upon detecting misprediction  
Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register...
8555039 System and method for using a local condition code register for accelerating conditional instruction execution in a pipeline processor  
A method of executing a conditional instruction within a pipeline processor having a plurality of pipelines, the processor having a first condition code register associated with a first pipeline...
8539500 Efficient partial execution for the parallelization of software analysis in a distributed computing environment  
An electronic device includes a memory, a processor coupled to the memory, and one or more policies stored in the memory. The policies include a resource availability policy determining whether...
8527743 Simultaneous checking of plural exit conditions loaded in table subsequent to execution of wait instruction for jitter free exit  
A microprogrammable electronic device comprises a code memory storing a plurality of instructions. At least one instruction, when executed by the device, causes the device to enter into a wait...
8521997 Conditional execution with multiple destination stores  
A method for conditionally performing a SIMD operation causing a predetermined number of result objects to be held in a combination of different ones of a plurality of destination stores, the...
8521999 Executing touchBHT instruction to pre-fetch information to prediction mechanism for branch with taken history  
A method comprising receiving a branch instruction, decoding a branch address and the branch instruction, executing a branch action associated with the branch address, determining whether a branch...
8521996 Pipelined microprocessor with fast non-selective correct conditional branch instruction resolution  
A microprocessor includes a pipeline of stages for processing instructions and first and second types of conditional branch instruction includable by a program. The microprocessor makes a...
8516229 Two pass test case generation using self-modifying instruction replacement  
A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent...
8495734 Method and device for detecting an erroneous jump during program execution  
The present disclosure relates to a method for executing, by a processor, a program read in a program memory, comprising steps of: detecting a program memory read address jump; providing prior to...
8495591 Parsing of declarations in all branches of preprocessor conditionals  
Declarations from an input source code are serialized into a stream of tokens produced by following each branch of a preprocessor conditional directive statement that interrupts a declaration....
8489866 Branch trace history compression  
A method, data processing system, and computer program product for managing a branch trace environment. In response to a branch being taken for a first branch instruction that is conditional and...
8473725 System and method for processing interrupts in a computing system  
A system, processor and method are provided for digital signal processing. A processor may initiate processing a sequence of instructions followed by an interrupt. Each instruction may be...
8418154 Fast vector masking algorithm for conditional data selection in SIMD architectures  
Techniques are disclosed for generating fast vector masking SIMD code corresponding to source code having a conditional statement, where the SIMD code replaces the conditional statements with...
8392893 Emulation method and computer system  
The computer system of the present invention emulates target instructions. The computer system includes a processing unit for branching to collective emulation coding for emulating plural of...
8387053 Method and system for enhancing computer processing performance  
A method of performing operations in a computer system, computer system, and related method of compilation, are disclosed. In one embodiment, the method of performing includes providing compiled...
8381192 Software testing using taint analysis and execution path alteration  
Some embodiments of the present invention provide a system that tests a software program. During operation, the system traces a flow of tainted data through the software program during execution...
8332622 Branching to target address by adding value selected from programmable offset table to base address specified in branch instruction  
Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition...
8312254 Indirect function call instructions in a synchronous parallel thread processor  
An indirect branch instruction takes an address register as an argument in order to provide indirect function call capability for single-instruction multiple-thread (SIMT) processor architectures....
8296750 Optimization of a target program  
A method and apparatus for optimizing a target program including a pattern of instructions to be replaced. The method is performed by execution of program code by a processor of an information...
8285976 Method and apparatus for predicting branches using a meta predictor  
A branch predicting apparatus is disclosed that reduces branch mispredictions in a processor. The branch prediction apparatus includes a base misprediction history register. The branch prediction...
8275978 Execution of conditional branch instruction specifying branch point operand to be stored in jump stack with branch destination for jumping to upon matching program counter value  
In one embodiment the present invention includes a microprocessor that has a pipeline circuit, a branch circuit, and a control circuit. The pipeline circuit pipelines instructions for the...
8225077 Obfuscation device for generating a set of obfuscated instructions, processing device, method, program, and integrated circuit thereof  
An obfuscation device includes a first instruction generating unit, for each of a first process and a second process, which generates an initialization instruction for securing a management area...
8225012 Dynamic allocation of a buffer across multiple clients in a threaded processor  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
8190854 System and method of processing data using scalar/vector instructions  
A method of processing data is disclosed that includes performing a fetch of a plurality of instructions from a memory unit. The method also includes grouping the plurality of instructions into...
8161267 Methods and apparatus for scalable array processor interrupt detection and response  
Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution...

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