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7620804 |
Central processing unit architecture with multiple pipelines which decodes but does not execute both branch paths
A central processing unit (CPU) architecture with enhanced branch execution, being substantially a pipelined CPU with multiple pipelines, each pipeline having a plurality of stages, by which all...
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7617387 |
Methods and system for resolving simultaneous predicted branch instructions
A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions,...
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7613910 |
Information processing apparatus, method, and computer-readable recording medium for replacing an entry in a memory device
The present invention relates to an information processing apparatus predicting a branch destination of a branch instruction using a branch history register to realize effective replacement by...
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7603545 |
Instruction control method and processor to process instructions by out-of-order processing using delay instructions for branching
An instruction control method carries out an instruction in a processor to process instructions by out-of-order processing, using delay instructions for branching. The processor includes a storage...
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7603544 |
Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
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7600102 |
Condition bits for controlling branch processing
A processing pipeline with a plurality of pipeline stages is described, with the processing pipeline comprising a front end and a back end. The processing pipeline's front end comprises an array...
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7581088 |
Conditional execution using an efficient processor flag
Methods and apparatus are provided for optimizing a conditional execution on a processor core. A processor sets a flag based on both the result and the type of an instruction. The flag is used...
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7543136 |
System and method for managing divergent threads using synchronization tokens and program instructions that include set-synchronization bits
One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The...
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7539851 |
Using register readiness to facilitate value prediction
One embodiment of the present invention provides a system for using register readiness to facilitate value prediction. The system starts by loading a previously computed result for a function to a...
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7526760 |
Methods for implementing virtual method invocation with shared code
A method for implementing virtual method invocation when a compiled code of an invoked method is shared between class types that share a runtime representation is provided. In this method, an entry...
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7519777 |
Methods, systems and computer program products for concomitant pair prefetching
Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride...
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7493615 |
Apparatus and method for synchronizing multiple threads in an out-of-order microprocessor
The present invention generally relates to synchronization of multiple threads in an out-of-order microprocessor utilizing the insertion of a trap. In one embodiment, while synchronizing multiple...
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7434036 |
System and method for executing software program instructions using a condition specified within a conditional execution instruction
A processor is disclosed including an instruction unit and an execution unit. The instruction unit fetches and decodes instructions, including a conditional execution instruction. The conditional...
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7428632 |
Branch prediction mechanism using a branch cache memory and an extended pattern cache
A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a...
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7421572 |
Branch instruction for processor with branching dependent on a specified bit in a register
A processor such as a parallel hardware-based multithreaded processor ( 12 ) is described. The processor ( 12 ) can execute a computer instruction that is a branch instruction that causes an...
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7418578 |
Simultaneously assigning corresponding entry in multiple queues of multi-stage entries for storing condition attributes for validating simultaneously executed conditional execution instruction groups
A processor is disclosed including several features allowing the processor to simultaneously execute instructions of multiple conditional execution instruction groups. Each conditional execution...
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7415602 |
Apparatus and method for processing a sequence of jump instructions
An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an...
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7406613 |
Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions
In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder...
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7398373 |
System and method for processing complex computer instructions
A system and method for handling complex instructions are provided. The process includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting...
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7389405 |
Digital signal processor architecture with optimized memory access for code discontinuity
A method and architecture accesses a unified memory in a micro-processing system having a two-phase clock. The unified memory is accessed during a first instruction cycle. When a program code...
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7370182 |
Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor
A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program...
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7350061 |
Assigning free register to unmaterialized predicate in inverse predicate expression obtained for branch reversal in predicated execution system
Described is a method that identifies a predicate expression representing conditions in predicated assembly language instructions that determine a direction of a conditional branch instruction. The...
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7340592 |
Executing a translated block of instructions and branching to correction code when expected top of stack does not match actual top of stack to adjust stack at execution time to continue executing without restarting translating
A method of generating an expected TOS during translation of instructions. The method includes translating a first block of instructions executable in a first processor architecture, into a...
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7337306 |
Executing conditional branch instructions in a data processor having a clustered architecture
There is disclosed a data processor having a clustered architecture that comprises at least one branching cluster, at least one non-branching cluster and remote conditional branching control...
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7322027 |
Detecting termination and providing information related to termination of a computer system process
The present invention extends to mechanisms for detecting termination and providing information related to termination of a computer system process. A computer system loads a termination function...
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7318228 |
System and method for task arbitration in multi-threaded simulations
Present herein is a system and method for arbitration in multi-threaded programming. Task calls are directed to a task wrapper that associates the task call with a particular unique identifier, and...
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7302556 |
Method, apparatus and computer program product for implementing level bias function for branch prediction control for generating test simulation vectors
A method, apparatus and computer program product are provided for implementing a level bias function for branch prediction control for generating test simulation vectors. User selected options are...
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7302555 |
Zero overhead branching and looping in time stationary processors
Programmable processors are used to transform input data into output data based on program information encoded in instructions. The value of the resulting output data depends, amongst others, on...
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7296141 |
Method for cancelling speculative conditional delay slot instructions
A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. The...
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7281122 |
Method and apparatus for nested control flow of instructions using context information and instructions having extra bits
A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction...
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7278014 |
System and method for simulating hardware interrupts
A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a “no operation” (or NOOP) instruction would normally be inserted....
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7272704 |
Hardware looping mechanism and method for efficient execution of discontinuity instructions
A hardware looping mechanism and method is described herein for handling any number and/or type of discontinuity instruction that may arise when executing program instructions within a scalar or...
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7260704 |
Method and apparatus for reinforcing a prefetch chain
A content prefetcher having a prefetch chain reinforcement mechanism. In response to a prefetch hit at a cache line within a prefetch chain, a request depth of the hit cache line is promoted and...
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7257665 |
Branch-aware FIFO for interprocessor data sharing
A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations...
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7251808 |
Graphical debugger with loadmap display manager and custom record display manager displaying user selected customized records from bound program objects
Enhanced graphical user interface functions are provided in a graphical debugger. A user interface operatively controls a graphical user interface. A loadmap display manager coupled to the user...
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7251721 |
Conditional link pointer register sets marking the beginning and end of a conditional instruction block where each set corresponds to a single stage of a pipeline that moves link pointers through each corresponding register of said register sets as instructions move through the pipeline
For use in a wide-issue processor, a mechanism for, and method of, conditionally executing instructions and a digital signal processor (DSP) incorporating the mechanism or the method. In one...
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7243350 |
Speculative execution for java hardware accelerator
Conditional branch bytecodes are processed by a Virtual Machine Interpreter (VMI) hardware accelerator that utilizes a branch prediction scheme to determine whether to speculatively process...
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7237098 |
Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence
A microprocessor for predicting a target address of a return instruction is disclosed. The microprocessor includes a BTAC and a return stack that each makes a prediction of the target address....
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7219279 |
Software testing
A system and method for generating executable units suitable for unit testing of a module for integration errors, the method comprising; recording, for a module, an interface specification that...
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7210024 |
Conditional instruction execution via emissary instruction for condition evaluation
Hazard detection is simplified by converting a conditional instruction, operative to perform an operation if a condition is satisfied, into an emissary instruction operative to evaluate the...
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7203936 |
Determining guarding predicate from partition graph based deduction to generate inverse predicate expression for branch reversal
Described is a method that identifies a predicate expression representing conditions in predicated assembly language instructions that determine a direction of a conditional branch instruction. The...
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7203827 |
Link and fall-through address formation using a program counter portion selected by a specific branch address bit
A link address/sequential address generation circuit is provided for generating a link/sequential address. The circuit receives the most significant bits of at least two addresses: a first address...
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7178012 |
Semiconductor device
An object of the present invention is to provide a semiconductor device that can prevent performance degradation due to wasted execution cycles. According to the present invention, a fetch is...
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7167973 |
Method and system for performing multi-tests in processors using results to set a register and indexing based on the register
A microprocessor, including a plurality of registers and an instruction execution module which is adapted to process a sequence of conditional tests. The module uses an instruction set that has the...
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7139902 |
Implementation of an efficient instruction fetch pipeline utilizing a trace cache
A method and apparatus are disclosed for enhancing the pipeline instruction transfer and execution performance of a computer architecture by reducing instruction stalls due to branch and jump...
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7103882 |
Optimization apparatus, complier program, optimization method and recording medium
An optimization apparatus (compiler program, method and recording medium) for changing the order of execution of instructions in a program to be optimized includes an exception occasion instruction...
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7100023 |
System and method for processing complex computer instructions
A system and method for handling complex instructions includes generating a jump instruction from an address which may be embedded in a computer instruction and selecting the original instruction...
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7080238 |
Non-blocking, multi-context pipelined processor
A packet processor whose processing capabilities are optimized by concurrently processing multiple packets within various pipelined stages. At each stage, multiple packets are processed via an...
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7062639 |
Method and apparatus for performing predicate prediction
In one method, a predicted predicate value for a predicate is determined. A predicated instruction is then conditionally executed depending on the predicted predicate value.
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7039776 |
Patch memory system for a ROM-based processor
An embedded ROM-based processor system including a processor, system memory, a programmable memory, a data selector and a patch controller. The system memory includes a read-only memory (ROM). The...
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