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7620803 Data processing device and electronic equipment using pipeline control  
A data processing device is provided using pipeline architecture to reduce a time loss due to a branch without causing an increase in circuit scale. The data processing device uses pipeline...
7613907 Embedded software camouflage against code reverse engineering  
Methods and apparatus for identifying a first flow control instruction in an executing program, the first instruction being associated with a first program address at which program execution will...
7607133 Interrupt processing control  
A data processing system 2 supporting interrupt handling is provided with an interrupt controller 24 . The interrupt controller is responsive to save state data when interrupt processing is...
7603544 Dynamic allocation of a buffer across multiple clients in multi-threaded processor without performing a complete flush of data associated with allocation  
A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using...
7590832 Information processing device, compressed program producing method, and information processing system  
An information processing device for executing a compressed program includes: an instruction buffer; a first selector for selectively outputting one of a set of signals obtained by dividing the...
7587532 Full/selector output from one of plural flag generation count outputs  
A method and apparatus for adaptive buffer sizing adjusts the size of the buffer at different levels using a “high water mark” to different levels for different system conditions. The high...
7574586 Efficient transfer of branch information  
A system comprising a processor adapted to execute software code comprising branch instructions and a trace logic coupled to the processor and adapted to generate a branch packet comprising branch...
7539853 Handling interrupts in data processing of data in which only a portion of a function has been processed  
A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the...
7529914 Method and apparatus for speculative execution of uncontended lock instructions  
A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will...
7519777 Methods, systems and computer program products for concomitant pair prefetching  
Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride...
7503049 Information processing apparatus operable to switch operating systems  
An information processing apparatus switches between an Operating System 1 and an Operating System 2 during operation and comprises: a storing unit including a first area storing data managed...
7493479 Method and apparatus for event detection for multiple instruction-set processor  
A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device...
7487334 Branch encoding before instruction cache write  
Method, system and computer program product for determining the targets of branches in a data processing system. A method for determining the target of a branch in a data processing system includes...
7477255 System and method for synchronizing divergent samples in a programmable graphics processing unit  
A method for synchronizing divergent samples in a programmable graphics processing unit is described. In one embodiment, the method includes the steps of determining that a divergence has occurred...
7472384 System, method and computer program product for on-the-fly patching of executable code  
On-the-fly patching of executable code includes placing a block of modified instructions in memory, identifying a block of code to be patched, storing instructions to be patched from the block of...
7472261 Method for performing externally assisted calls in a heterogeneous processing complex  
A method is provided for accessing, by an application running on a first processor, operating system services from an operating system running on a second processor by performing an assisted call....
7434035 Method and system for processing instructions in grouped and non-grouped modes  
An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor...
7428632 Branch prediction mechanism using a branch cache memory and an extended pattern cache  
A branch prediction mechanism includes a branch prediction memory and an extended pattern cache. The extended pattern cache detects predetermined repeating patterns of branch outcomes and stores a...
7415601 Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters  
A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for...
7412592 Branch instruction control apparatus and control method  
The branch instruction control apparatus of the present invention is a control apparatus in which a plurality of entries in which data required for the implementation control of the branch...
7386647 System and method for processing an interrupt in a processor supporting multithread execution  
A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to...
7370182 Method of handling branching instructions within a processor, in particular a processor for digital signal processing, and corresponding processor  
A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program...
7363477 Method and apparatus to reduce misprediction penalty by exploiting exact convergence  
A method and apparatus for executing a selective recovery after a branch misprediction is disclosed. In one embodiment, the instructions following the mispredicted branch point may be saved for...
7350061 Assigning free register to unmaterialized predicate in inverse predicate expression obtained for branch reversal in predicated execution system  
Described is a method that identifies a predicate expression representing conditions in predicated assembly language instructions that determine a direction of a conditional branch instruction. The...
7340628 Branch based activity monitoring  
During execution of a program of computer instructions, the execution of branch instructions is detected, and in response, the activity of processing circuitry during execution of instructions...
7340588 Extending the number of instruction bits in processors with fixed length instructions, in a manner compatible with existing code  
This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code...
7318145 Random slip generator  
A random slip generator is provided to lessen side channel leakage and thus thwart cryptanalysis attacks, such as timing attacks and power analysis attacks. Random slip generation may be...
7308562 System and method for improved branch performance in pipelined computer architectures  
A system and method for improved branch performance in pipelined computer architectures is presented. Priority bits are set during code execution that corresponds to an upcoming branch instruction....
7302556 Method, apparatus and computer program product for implementing level bias function for branch prediction control for generating test simulation vectors  
A method, apparatus and computer program product are provided for implementing a level bias function for branch prediction control for generating test simulation vectors. User selected options are...
7296141 Method for cancelling speculative conditional delay slot instructions  
A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. The...
7284116 Method and system for safe data dependency collapsing based on control-flow speculation  
The present invention is directed to an apparatus and method for data collapsing based on control-flow speculation (conditional branch predictions). Because conditional branch outcomes are resolved...
7281122 Method and apparatus for nested control flow of instructions using context information and instructions having extra bits  
A method and apparatus for nested control flow includes a processor having at least one context bit. The processor includes a plurality of arithmetic logic units for performing single instruction...
7278062 Method and apparatus for responding to access errors in a data processing system  
In one embodiment, a data processing system ( 10 ) has a processor ( 14 ) coupled to a bus, where the data processing system ( 10 ) includes access error detection circuitry ( 26 ) and access error...
7278011 Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion table  
A method, completion table and processor for tracking a larger number of outstanding instructions. The completion table may include a plurality of entries where each entry tracks a consecutive...
7272748 Method and apparatus to detect and recover from a stack frame corruption  
A prologue and an epilogue of a function are hooked. Completion of the prologue is stalled in a first state of a stack frame, and a copy of the first state of the stack frame is saved. Completion...
7272704 Hardware looping mechanism and method for efficient execution of discontinuity instructions  
A hardware looping mechanism and method is described herein for handling any number and/or type of discontinuity instruction that may arise when executing program instructions within a scalar or...
7266676 Method and apparatus for branch prediction based on branch targets utilizing tag and data arrays  
Methods and apparatus are provided for branch prediction in a digital processor. A method includes providing a branch target buffer having a tag array and a data array, wherein each entry in the...
7260705 Apparatus to implement mesocode  
In one embodiment, the invention provides a method for examining information about branch instructions. A method, comprising: examining information about branch instructions that reach a write-back...
7260704 Method and apparatus for reinforcing a prefetch chain  
A content prefetcher having a prefetch chain reinforcement mechanism. In response to a prefetch hit at a cache line within a prefetch chain, a request depth of the hit cache line is promoted and...
7257665 Branch-aware FIFO for interprocessor data sharing  
A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations...
7254689 Decompression of block-sorted data  
In an embodiment of the present invention, the computational efficiency of decoding of block-sorted compressed data is improved by ensuring that more than one set of operations corresponding to a...
7243350 Speculative execution for java hardware accelerator  
Conditional branch bytecodes are processed by a Virtual Machine Interpreter (VMI) hardware accelerator that utilizes a branch prediction scheme to determine whether to speculatively process...
7237098 Apparatus and method for selectively overriding return stack prediction in response to detection of non-standard return sequence  
A microprocessor for predicting a target address of a return instruction is disclosed. The microprocessor includes a BTAC and a return stack that each makes a prediction of the target address....
7228528 Building inter-block streams from a dynamic execution trace for a program  
In one embodiment, the invention provides a method for the processing of instructions. A method which comprises analyzing a dynamic execution trace for a program; identifying at least one stream...
7222064 Instruction processor emulation having inter-processor messaging accounting  
Techniques are described for emulating inter-processor communications between multiple instruction processors. The techniques provide inter-processor message accounting and error detection. A...
7219216 Method for identifying basic blocks with conditional delay slot instructions  
A first tag is assigned to a branch instruction. Dependent on the type of branch instruction, a second tag is assigned to an instruction in the branch delay slot of the branch instruction. If the...
7197630 Method and system for changing the executable status of an operation following a branch misprediction without refetching the operation  
A method and system for changing the executable status of an operation following a branch misprediction. In one embodiment, a method may include predicting an execution path of a first conditional...
7194609 Branch reconfigurable systems and methods  
The invention is a system and method for executing programs. The invention involves a plurality of processing elements, wherein a processing element of the plurality of processing elements...
7188337 Interrupt program module  
A computer implemented method to be implemented by a computer, which sequentially consecutively performs a plurality of predetermined process, when the computer receives an interrupt request to...
7181597 Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation module  
A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A...
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